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PDF CLC031 Data sheet ( Hoja de datos )

Número de pieza CLC031
Descripción SMPTE 292M/259M Digital Video Deserializer / Descrambler
Fabricantes National Semiconductor 
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PRELIMINARY
August 2003
CLC031
SMPTE 292M/259M Digital Video Deserializer /
Descrambler with Video and Ancilliary Data FIFOs
General Description
The CLC031 SMPTE 292M / 259M Digital Video
Deserializer/Descrambler with Video and Ancilliary Data
FIFOs is a monolithic integrated circuit that deserializes and
decodes SMPTE 292M, 1.485Gbps (or 1.483Gbps) serial
component video data, to 20-bit parallel data with a synchro-
nized parallel word-rate clock. It also deserializes and de-
codes SMPTE 259M, 270Mbps, 360Mbps and
SMPTE 344M (proposed) 540Mbps serial component video
data, to 10-bit parallel data. Functions performed by the
CLC031 include: clock/data recovery from the serial data,
serial-to-parallel data conversion, SMPTE standard data de-
coding, NRZI-to-NRZ conversion, parallel data clock genera-
tion, word framing, CRC and EDH data checking and han-
dling, ancilliary data extraction and automatic video format
determination. The parallel video output features a variable-
depth FIFO which can be adjusted to delay the output data
up to 4 parallel data clock periods. Ancilliary data may be
selectively extracted from the parallel data through the use
of masking and control bits in the configuration and control
registers and stored in the on-chip FIFO. Reverse LSB dith-
ering is also implemented.
The unique multi-functional I/O port of the CLC031 provides
external access to functions and data stored in the configu-
ration and control registers. This feature allows the designer
greater flexibility in tailoring the CLC031 to the desired ap-
plication. The CLC031 is auto-configured to a default oper-
ating condition at power-on or after a reset command. Sepa-
rate power pins for the PLL, deserializer and other functional
circuits improve power supply rejection and noise perfor-
mance.
The CLC031 has a unique Built-In Self-Test (BIST) and
video Test Pattern Generator (TPG). The BIST enables com-
prehensive testing of the device by the user. The BIST uses
the TPG as input data and includes SD and HD component
video test patterns, reference black, PLL and EQ pathologi-
cals and a 75% saturation, 8 vertical colour bar pattern, for
all implemented rasters. The colour bar pattern has optional
transition coding at changes in the chroma and luma bar
data. The TPG data is output via the parallel data port.
The CLC030, SMPTE 292M / 259M Digital Video Serializer
with Ancilliary Data FIFO and Integrated Cable Driver, is the
ideal complement to the CLC031.
The CLC031’s internal circuitry is powered from +2.5 Volts
and the I/O circuitry from a +3.3 Volt supply. Power dissipa-
tion is typically 850mW. The device is packaged in a 64-pin
TQFP.
Features
n SDTV/HDTV serial digital video standard compliant
n Supports 270 Mbps, 360 Mbps, 540 Mbps, 1.483 Gbps
and 1.485 Gbps serial video data rates with
auto-detection
n LSB de-dithering option
n Uses low-cost 27MHz crystal or clock oscillator
reference
n Fast VCO lock time: < 500 µs at 1.485 Gbps
n Built-in self-test (BIST) and video test pattern generator
(TPG)*
n Automatic EDH/CRC word and flag processing
n Ancilliary data FIFO with extensive packet handling
options
n Adjustable, 4-deep parallel output video data FIFO
n Flexible control and configuration I/O port
n LVCMOS compatible control inputs and clock and data
outputs
n LVDS and ECL-compatible, differential, serial inputs
n 3.3V I/O power supply and 2.5V logic power supply
operation
n Low power: typically 850mW
n 64-pin TQFP package
n Commercial temperature range 0˚C to +70˚C
* Patent applications made or pending.
Applications
n SDTV/HDTV serial-to-parallel digital video interfaces for:
— Video editing equipment
— VTRs
— Standards converters
— Digital video routers and switchers
— Digital video processing and editing equipment
— Video test pattern generators and digital video test
equipment
— Video signal generators
Ordering Information
Order Number
CLC031VEC
Package Type
64-Pin TQFP
NS Package Number
VEC-64A
© 2003 National Semiconductor Corporation DS200201
www.national.com

1 page




CLC031 pdf
Absolute Maximum Ratings (Note 1)
It is anticipated that this device will not be offered in
a military qualified version. If Military/Aerospace speci-
fied devices are required, please contact the National
Semiconductor Sales Office / Distributors for availability
and specifications.
CMOS I/O Supply Voltage
(VDDIO– VSSIO):
SDI Supply Voltage
(VDDSI– VSSSI):
Digital Logic Supply Voltage
(VDDD– VSSD):
PLL Supply Voltage
(VDDPLL– VSSPLL):
CMOS Input Voltage
(Vi):
CMOS Output Voltage
(Vo):
4.0V
4.0V
3.0V
3.0V
VSSIO −0.15V to
VDDIO +0.15V
VSSIO −0.15V to
VDDIO +0.15V
CMOS Input Current (single input):
Vi = VSSIO −0.15V:
Vi = VDDIO +0.15V:
CMOS Output Source/Sink Current:
IBB Output Current:
IREF Output Current:
SDI Input Voltage
(Vi):
Package Thermal Resistance
θJA @ 0 LFM Airflow
θJA @ 500 LFM Airflow
θJC
Storage Temp. Range:
Junction Temperature:
Lead Temperature (Soldering 4
Sec):
ESD Rating (HBM):
ESD Rating (MM):
Recommended Operating Conditions
Symbol
VDDIO
VDDSD
VDDD
VDDPLL
TA
Parameter
CMOS I/O Supply Voltage
SDI Supply Voltage
Digital Logic Supply
Voltage
PLL Supply Voltage
Operating Free Air
Temperature
Conditions
VDDIO−VSSIO
VDDSI−VSSSI
VDDD– VSSD
VDDPLL– VSSPLL
Reference
Min
3.150
Typ
3.300
2.375 2.500
0
Required Input Conditions
(Note 9)
Symbol
VIN
tr, tf
Parameter
Input Voltage Range
Rise Time, Fall Time
BRSDI
Serial Input Data Rate
VCM(SDI)
VIN(SDI)
Common Mode Voltage
SDI Serial Input Voltage
tr, tf Rise Time, Fall Time
Conditions
10%–90%
SMPTE 259M, Level C
SMPTE 259M, Level D
SMPTE 344M
SMPTE 292M
SMPTE 292M
VIN = 100 mV
Reference
All LVCMOS
Inputs
SDI, SDI
20%–80%, SMPTE 259M
Data Rates
20%–80%, SMPTE 292M
Data Rates
SDI, SDI
Min
VSSIO
1.0
VSSSI
+0.05V
100
720
Typ
1.5
270
360
540
1,483
1,485
800
800
−5 mA
+5 mA
±6 mA
+300 µA
+300 µA
VSSSI −0.15V to
VDDSI +0.15V
40.1˚C/W
24.5˚C/W
5.23˚C/W
−65˚C to +150˚C
+150˚C
+260˚C
>2.5 kV
>250 V
Max
3.450
Units
V
2.625
V
+70 ˚C
Max
VDDIO
3.0
Units
V
ns
MBPS
VDDSI
−0.05V
880
880
270
V
mV
ps
5 www.national.com

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CLC031 arduino
Device Operation (Continued)
20020106
FIGURE 1. Optional Input Biasing Scheme
The SMPTE descrambler receives NRZI serial data, con-
verts it to NRZ, then decodes it to either 10-bit standard
definition or 20-bit high definition parallel video data using
the reverse polynomial X9 + X4 + 1 as specified in the
respective standard: SMPTE 259M, SMPTE 344M (pro-
posed) or SMPTE 292M. The data reception bit order is
LSB-first. All data processing is done at the parallel rate.
The CLC031 incorporates circuitry that implements a
method for handling data that has been subjected to LSB
dithering. When so enabled, data from the de-scrambler is
routed for de-dithering. The De-Dither Enable bit in the
VIDEO INFO 0 control register enables this function. De-
dithering of data present in the vertical blanking interval can
be selectively enabled by use of the V De-Dither Enable bit
in the VIDEO INFO 0 control register. The initial condition of
De-Dither Enable and V De-Dither Enable is OFF.
The descrambler supplies signals to theTRS character de-
tector which identifies the presence of the valid video data.
The TRS character detector processes the timing refer-
ence signals which control raster framing. TRS (sync) char-
acters are detected and the video is aligned on word bound-
aries. Data is re-synchronized with the parallel word-rate
clock. Interraction and operation of the character alignment
control signals and indicators Framing Mode, Framing En-
able and NSP (New Sync Position) is described later in this
datasheet.
The CLC031 implements TRS character LSB-clipping as
prescribed in ITU-R BT.601. LSB-clipping causes all TRS
characters with a value between 000h and 003h to be forced
to 000h and all TRS characters with a value between 3FCh
and 3FFh to be forced to 3FFh. Clipping is done after de-
scrambling and de-dithering.
Once the PLL attains lock, the video format detector pro-
cesses the received data to determine the raster character-
istics (video data format) and configure the CLC031 to
handle it. This assures that the parallel output data will be
properly formatted, that the correct data rate is selected and
that ancilliary data and CRC/EDH data are correctly de-
tected and checked. Supported parallel data formats or sub-
formats may belong to any one of several component stan-
dards: SMPTE 125M, SMPTE 267M, SMPTE 260M, 274M,
295M or 296M. Refer to Table 4 for the supported formats.
(See also the Application Information section for handling of
other raster formats or format extensions developed after
this device was designed). The detected video standard
information is passed to the device control system and
saved in the control registers from whence it may be read by
the user.
The CLC031 may be configured to operate in a single video
format by loading the appropriate FORMAT SET[4:0] control
data into the FORMAT 0 control register. Also, the CLC031
may be configured to handle only the standard-definition
data formats by setting the SD ONLY bit or only the high-
definition data formats by setting the HD ONLY bit in the
FORMAT 0 control register. When both bits are reset, the
default condition, the part automatically detects the data rate
and range.
Aligned and de-processed parallel data passes into a
variable-depth video FIFO prior to output. Video FIFO depth
from 0 to 4 registers is set by a 3-bit word written into the
VIDEO FIFO Depth[2:0] bits in the ANC 0 control register.
The video FIFO permits adjustment of the parallel video data
output timing or delay at a parallel word rate. The occurence
of corresponding TRS indicator bits, EAV, SAV and NSP, in
the control register corresponds to the input register position
of the FIFO. This positioning permits a look-ahead function
in which the alignment status of the video data can be
determined up to four parallel clock periods prior to the
appearance of that data at the parallel data output.
The parallel video data is output on DV[19:0]. The 20-bit
parallel video data is organized so that for HDTV data, the
upper-order 10 bits DV[19:10] are luminance (luma) infor-
mation and the lower 10 bits DV[9:0] are colour difference
(chroma) information. SDTV data use the lower-order 10-bits
DV[9:0] for both luma and chroma information. (The SDTV
parallel data is also duplicated on DV[19:10]). VCLK is the
parallel output word rate clock signal. The frequency of VCLK
is appropriate to either the HD or SD data being processed.
Data is valid between the falling edges of a VCLK cycle. Data
may be clocked into external devices on the rising-edge of
VCLK. The DV[19:0] and VCLK signals are LVCMOS-
compatible.
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