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PDF PCK9448 Data sheet ( Hoja de datos )
| Número de pieza | PCK9448 | |
| Descripción | LVCMOS 1 : 12 clock fan-out buffer | |
| Fabricantes | NXP Semiconductors | |
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PCK9448
3.3 V/2.5 V LVCMOS 1 : 12 clock fan-out buffer
Rev. 01 — 29 November 2005
Product data sheet
1. General description
The PCK9448 is a 3.3 V or 2.5 V compatible, 1 : 12 clock fan-out buffer targeted for high
performance clock tree applications. With output frequencies up to 350 MHz and output
skews less than 150 ps, the device meets the needs of most demanding clock
applications.
The PCK9448 is specifically designed to distribute LVCMOS compatible clock signals up
to a frequency of 350 MHz. Each output provides a precise copy of the input signal with
near zero skew. The output buffers support driving of 50 Ω terminated transmission lines
on the incident edge: each is capable of driving either one parallel terminated or two
series terminated transmission lines.
Two selectable independent clock inputs are available, providing support of LVCMOS and
differential LVPECL clock distribution systems. The PCK9448 CLK_STOP control is
synchronous to the falling edge of the input clock. It allows the start and stop of the output
clock signal only in a logic LOW state, thus eliminating potential output runt pulses.
Applying the OE control will force the outputs into high-impedance mode.
All inputs have an internal pull-up or pull-down resistor preventing unused and open inputs
from floating. The device supports a 2.5 V or 3.3 V power supply and an ambient
temperature range of −40 °C to +85 °C.
2. Features
s 12 LVCMOS compatible clock outputs
s Selectable LVCMOS and differential LVPECL compatible clock inputs
s Maximum clock frequency of 350 MHz
s Maximum clock skew of 150 ps
s Synchronous output stop in logic LOW state eliminates output runt pulses
s High-impedance output control
s 3.3 V or 2.5 V power supply
s Drives up to 24 series terminated clock lines
s Tamb = −40 °C to +85 °C
s Available in LQFP32 package
s Supports clock distribution in networking, telecommunications, and computer
applications
1 page  
Philips Semiconductors
PCK9448
3.3 V/2.5 V LVCMOS 1 : 12 clock fan-out buffer
8.2 Static characteristics
Table 6: Static characteristics (3.3 V)
Tamb = −40 °C to +85 °C; VCC = 3.3 V ± 5 %; unless otherwise specified.
Symbol Parameter
Conditions
VIH
VIL
VOH
VOL
Vi(p-p)
VICR [1]
HIGH-state input voltage
LOW-state input voltage
HIGH-state output voltage
LOW-state output voltage
peak-to-peak input voltage (PCLK)
common-mode input voltage range
(PCLK)
LVCMOS
LVCMOS
IOH = −24 mA
IOL = 24 mA
IOL = 12 mA
LVPECL
LVPECL
Zo
II
Iq(max)
output impedance
input current
maximum quiescent current
VI = VCC or GND
all VCC pins
Min
2.0
−0.3
[2] 2.4
[2] -
-
250
1.1
-
[3] -
[4] -
Typ
-
-
-
-
-
-
-
17
-
-
Max
VCC + 0.3
+0.8
-
0.55
0.30
-
VCC − 0.6
Unit
V
V
V
V
V
mV
V
-Ω
300 µA
2.0 mA
[1] VICR (DC) is the cross point of the differential input signal. Functional operation is obtained when the cross point is within the VICR range
and the input swing lies within the Vi(p-p) (DC) specification.
[2] The PCK9448 is capable of driving 50 Ω transmission lines on the incident edge. Each output drives one 50 Ω parallel terminated
transmission line to a termination voltage of VT. Alternatively, the device drives up to two 50 Ω series terminated transmission lines
(VCC = 3.3 V) or one 50 Ω series terminated transmission line (for VCC = 2.5 V).
[3] Inputs have pull-down or pull-up resistors affecting the input current.
[4] Iq(max) is the DC current consumption of the device with all outputs open and the input in its default state or open.
Table 7: Static characteristics (2.5 V)
Tamb = −40 °C to +85 °C; VCC = 2.5 V ± 5 %; unless otherwise specified.
Symbol Parameter
Conditions
VIH
VIL
VOH
VOL
Vi(p-p)
VICR [1]
HIGH-state input voltage
LOW-state input voltage
HIGH-state output voltage
LOW-state output voltage
peak-to-peak input voltage (PCLK)
common-mode input voltage range
(PCLK)
LVCMOS
LVCMOS
IOH = −15 mA
IOL = 15 mA
LVPECL
LVPECL
Zo
II
Iq(max)
output impedance
input current
maximum quiescent current
VI = VCC or GND
all VCC pins
Min
1.7
−0.3
[2] 1.8
-
250
1.0
-
[3] -
[4] -
Typ
-
-
-
-
-
-
19
-
-
Max
VCC + 0.3
+0.7
-
0.6
-
VCC − 0.7
Unit
V
V
V
V
mV
V
-Ω
300 µA
2.0 mA
[1] VICR (DC) is the cross point of the differential input signal. Functional operation is obtained when the cross point is within the VICR range
and the input swing lies within the Vi(p-p) (DC) specification.
[2] The PCK9448 is capable of driving 50 Ω transmission lines on the incident edge. Each output drives one 50 Ω parallel terminated
transmission line to a termination voltage of VT. Alternatively, the device drives one 50 Ω series terminated transmission line per output
at VCC = 2.5 V.
[3] Inputs have pull-down or pull-up resistors affecting the input current.
[4] Iq(max) is the DC current consumption of the device with all outputs open and the input in its default state or open.
9397 750 12534
Product data sheet
Rev. 01 — 29 November 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
5 of 20
5 Page 
Philips Semiconductors
PCK9448
3.3 V/2.5 V LVCMOS 1 : 12 clock fan-out buffer
The waveform plots of Figure 13 show simulation results of an output driving a single line
versus two lines. In both cases the drive capability of the PCK9448 output buffer is more
than sufficient to drive 50 Ω transmission lines on the incident edge. Note from the delay
measurement in the simulations a delta of only 43 ps exists between the two differently
loaded outputs. This suggests that the dual line driving need not be used exclusively to
maintain the tight output-to-output skew of the PCK9448. The output waveform in
Figure 13 shows a step in the waveform; this step is caused by the impedance mismatch
seen looking into the driver. The parallel combination of the 33 Ω series resistor plus the
output impedance does not match the parallel combination of the line impedances. The
voltage wave launched down the two lines will equal:
VL
=
V
S
-R---s----+-----RZ----oo---+-----Z----o-
Zo = 50 Ω || 50 Ω
Rs = 33 Ω || 33 Ω
Ro = 17 Ω
VL
=
3.0
1----6---.-5-----+--2--1-5--7-----+-----2---5-
=
1.28
V
At the load end the voltage will double, due to the near unity reflection coefficient, to 2.5 V.
It will then increment towards the quiescent 3.0 V in steps separated by one round trip
delay (in this case 4.0 ns).
3.0
voltage
(V)
2.0
IN
1.0
002aaa679
OutA
td = 3.8956 ns
OutB
td = 3.9386 ns
0
−0.5
0 4 8 12 16
time (ns)
Fig 13. Single versus dual line termination waveforms
Since this step is well above the threshold region it will not cause any false clock
triggering, however designers may be uncomfortable with unwanted reflections on the
line. To better match the impedances when driving multiple lines, the situation in Figure 14
should be used. In this case the series terminating resistors are reduced such that when
the parallel combination is added to the output buffer impedance the line impedance is
perfectly matched.
9397 750 12534
Product data sheet
Rev. 01 — 29 November 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
11 of 20
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet PCK9448.PDF ] | |
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