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PDF PCA9519 Data sheet ( Hoja de datos )
| Número de pieza | PCA9519 | |
| Descripción | 4-channel level translating I2C-bus/SMBus repeater | |
| Fabricantes | NXP Semiconductors | |
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PCA9519
4-channel level translating I2C-bus/SMBus repeater
Rev. 01 — 22 June 2006
Objective data sheet
1. General description
The PCA9519 is a 4-channel level translating I2C-bus/SMBus repeater that enables the
processor low voltage 2-wire serial bus to interface with standard I2C-bus or SMBus I/O.
While retaining all the operating modes and features of the I2C-bus system during the
level shifts, it also permits extension of the I2C-bus by providing bidirectional buffering for
both the data (SDA) and the clock (SCL) lines, thus enabling the I2C-bus or SMBus
maximum capacitance of 400 pF on the higher voltage side. The SDA and SCL pins are
over-voltage tolerant and are high-impedance when the PCA9519 is unpowered.
The port B drivers are compliant with SMBus I/O levels, while port A uses a current
sensing mechanism to detect the input or output LOW signal which prevents bus lock-up.
The port A uses a 1 mA current source for pull-up and a 200 Ω pull-down driver. This
results in a LOW on port A accommodating smaller voltage swings. The output pull-down
on the port A internal buffer LOW is set for approximately 0.2 V, while the input threshold
of the internal buffer is set about 50 mV lower than that of the output voltage LOW. When
the port A I/O is driven LOW internally, the LOW is not recognized as a LOW by the input.
This prevents a lock-up condition from occurring. The output pull-down on the port B
drives a hard LOW and the input level is set at 0.3 of SMBus or I2C-bus voltage level
which enables port B to connect to any other I2C-bus device or buffer.
The PCA9519 drivers are not enabled unless VCC(A) is above 0.8 V and VCC(B) is above
2.5 V. The enable (EN) pin can also be used to turn the drivers on and off under system
control. Caution should be observed to only change the state of the EN pin when the bus
is idle.
2. Features
I 4-channel (4 SCL/SDA pairs), bidirectional buffer isolates capacitance and allows
400 pF on port B of the device
I Voltage level translation from port A (1 V to VCC(B) − 1 V) to port B (3.0 V to 5.5 V)
I Requires no external pull-up resistors on lower voltage port A
I Active HIGH repeater enable input
I Open-drain inputs/outputs
I Lock-up free operation
I Supports arbitration and clock stretching across the repeater
I Accommodates Standard-mode and Fast-mode I2C-bus devices and multiple masters
I Powered-off high-impedance I2C-bus pins
I Operating supply voltage range of 1.0 V to VCC(B) − 1 V on port A, 3.0 V to 5.5 V on
port B
I 5 V tolerant B-side SCL and SDA and enable pins
1 page  
Philips Semiconductors
PCA9519
4-channel level translating I2C-bus/SMBus repeater
go below its VILc it will pull the port B LOW initially when the port A input transitions LOW
but port B will return HIGH, so it will not reproduce the port A input on port B. Such
applications should be avoided.
Port B is interoperable with all I2C-bus slaves, masters, and repeaters.
6.1 Enable
The EN pin is active HIGH and allows the user to select when the repeater is active. This
can be used to isolate a badly behaved slave on power-up until after the system power-up
reset. It should never change state during an I2C-bus operation because disabling during
a bus operation will hang the bus and enabling part way through a bus cycle could
confuse the I2C-bus parts being enabled.
The enable pin should only change state when the bus and the repeater port are in an idle
state to prevent system failures.
6.2 I2C-bus systems
As with the standard I2C-bus system, pull-up resistors are required to provide the logic
HIGH levels on the buffered bus (standard open-collector configuration of the I2C-bus).
The size of these pull-up resistors depends on the system. Each of the port A I/Os has an
internal pull-up current source and does not require the external pull-up resistor. The
port B is designed to work with Standard mode and Fast mode I2C-bus devices in addition
to SMBus devices. Standard mode I2C-bus devices only specify 3 mA output drive; this
limits the termination current to 3 mA in a generic I2C-bus system where Standard mode
devices and multiple masters are possible. Under certain conditions higher termination
currents can be used.
7. Application design-in information
A typical application is shown in Figure 4. In this example, the CPU is running on a 1.1 V
I2C-bus while the master is connected to a 3.3 V bus. Both buses run at 400 kHz. Master
devices can be placed on either bus.
1.1 V
3.3 V
SDA
SCL
CPU
1.1 V
10 kΩ
VCC(A)
10 kΩ
VCC(B)
A1
A2
PCA9519
B1
B2
A8 B8
EN
10 kΩ
SDA
SCL
MASTER
400 kHz
bus A
Fig 4. Typical application
bus B
002aab642
PCA9519_1
Objective data sheet
Rev. 01 — 22 June 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
5 of 17
5 Page 
Philips Semiconductors
12. Package outline
PCA9519
4-channel level translating I2C-bus/SMBus repeater
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
y
Z
20
D
c
11
EA
X
HE v M A
pin 1 index
1
e
10
wM
bp
A2
A1
Q
(A 3)
A
Lp
L
detail X
θ
0 2.5 5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
D (1) E (2)
e
6.6
6.4
4.5
4.3
0.65
HE
6.6
6.2
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
IEC
REFERENCES
JEDEC
JEITA
SOT360-1
MO-153
L Lp Q v w y Z (1) θ
1
0.75 0.4
0.50 0.3
0.2 0.13 0.1
0.5
0.2
8o
0o
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
Fig 11. Package outline SOT360-1 (TSSOP20)
PCA9519_1
Objective data sheet
Rev. 01 — 22 June 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
11 of 17
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet PCA9519.PDF ] | |
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