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PDF IP4771CZ16 Data sheet ( Hoja de datos )

Número de pieza IP4771CZ16
Descripción (IP4770CZ16 - IP4772CZ16) VGA/video interface
Fabricantes NXP Semiconductors 
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IP4770/71/72CZ16
VGA/video interface with integrated buffers, ESD protection
and integrated termination resistors
Rev. 01 — 25 October 2006
Product data sheet
1. General description
The IP4770CZ16, IP4771CZ16, IP4772CZ16 is connected between the VGA/DVI
interface and the video graphics controller and includes level shifting for the DDC signals,
buffering for the SYNC lines as well as high-level ESD protection diodes for the RGB
signal lines.
The level shifting functions are required when the DDC controller operates at a lower
supply voltage than the monitor. To use this level shifting function the gates of the two
N-channel MOSFETs have to be connected to the supply rail of the DDC transceivers.
Buffering for the SYNC signals is provided by two non-inverting buffers, which accept TTL
input levels and convert these to CMOS compliant output levels between pins VCC(SYNC)
and GND.
The IP4770CZ16 and IP4771CZ16 contain the formerly external termination resistors,
which are typically required for the HSYNC and VSYNC lines of the video interface:
IP4770CZ16: Rsync = 55
IP4771CZ16: Rsync = 65
IP4772CZ16: Rsync =10 to allow termination of the SYNC lines
All RGB I/Os are protected by a special diode configuration offering a low line capacitance
of 4 pF (maximum) only to provide protection to downstream components for ESD
voltages as high as ±8 kV contact discharge according to IEC 61000-4-2, level 4 standard.
2. Features
I Integrated high-level ESD protection, buffering, SYNC signal impedance matching and
level shifting
I Terminal connections with integrated rail-to-rail clamping diodes with downstream ESD
protection of ±8 kV according to IEC 61000-4-2, level 4 standard
I Backflow protection on DDC lines
I Drivers for HSYNC and VSYNC lines
I Bidirectional level shifting N-channel FETs available for DDC clock and DDC data
channels
I Integrated impedance matching resistors on SYNC lines
I Line capacitance < 4 pF per channel
I Lead-free package and RoHS compliant

1 page




IP4771CZ16 pdf
NXP Semiconductors
IP4770/71/72CZ16
VGA/video interface with ESD protection
8. Recommended operating conditions
Table 4.
Symbol
Toper
Recommended operating conditions
Parameter
operating temperature
Conditions
9. Characteristics
Table 5. Sync circuit characteristics
VCC(SYNC) = 5 V; Tamb = 25 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Supply: pin VCC(SYNC)
ICC(SYNC)
supply current on pin VCC(SYNC)
SYNC input at 3 V
Input: pins SYNC_IN1 and SYNC_IN2
VIH HIGH-level input voltage
VIL LOW-level input voltage
Output: pins SYNC_OUT1 and SYNC_OUT2
VOH
VOL
Rsync
HIGH-level output voltage
LOW-level output voltage
synchronization resistance
IOH = 1 mA
IP4772CZ16; IOH = 24 mA
IOL = 1 mA
IP4772CZ16; IOL = 24 mA
IP4770CZ16
IP4771CZ16
IP4772CZ16
Sync channel
tPLH LOW-to-HIGH propagation delay
tPHL HIGH-to-LOW propagation delay
tr(o) output rise time
tf(o) output fall time
Protection diode
CL = 50 pF; tr and tf 5 ns
CL = 50 pF; tr and tf 5 ns
CL = 50 pF; tr and tf 5 ns
CL = 7 pF; tr and tf 5 ns
CL = 50 pF; tr and tf 5 ns
CL = 7 pF; tr and tf 5 ns
IL(r)
VBRzd
VFd
reverse leakage current
Zener diode breakdown voltage
diode forward voltage
per channel; V = 3.0 V
I = 1 mA
IF = 1 mA
[1] SYNC outputs unloaded.
[2] Rsync = Rterm + Rbuffer.
[3] Rsync = Rbuffer because Rterm = 0 .
[4] This parameter is guaranteed by design and characterization.
Min Typ Max Unit
40 -
+85 °C
Min Typ Max Unit
[1] -
[1] -
- 50 µA
- 2 mA
2.0 -
--
-V
0.6 V
4.85
2.0
-
-
[2] -
[2] -
[3] -
-
-
-
-
55
65
10
-V
-V
0.15 V
0.8 V
-
-
-
[4] -
- 12 ns
[4] -
- 12 ns
- 4 - ns
- 1.5 - ns
- 4 - ns
- 1.5 - ns
- - 1 µA
6 -9 V
- 0.7 - V
IP4770CZ16_4771_4772_1
Product data sheet
Rev. 01 — 25 October 2006
© NXP B.V. 2006. All rights reserved.
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IP4771CZ16 arduino
NXP Semiconductors
16. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2
5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
8 Recommended operating conditions. . . . . . . . 5
9 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5
10 Application information. . . . . . . . . . . . . . . . . . . 7
11 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8
12 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . 9
14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 10
14.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 10
14.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
14.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
14.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
15 Contact information. . . . . . . . . . . . . . . . . . . . . 10
16 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
IP4770/71/72CZ16
VGA/video interface with ESD protection
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2006.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 25 October 2006
Document identifier: IP4770CZ16_4771_4772_1

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