DataSheet.es    


PDF NCP5214 Data sheet ( Hoja de datos )

Número de pieza NCP5214
Descripción Notebook DDR Power Controller
Fabricantes ON Semiconductor 
Logotipo ON Semiconductor Logotipo



Hay una vista previa y un enlace de descarga de NCP5214 (archivo pdf) en la parte inferior de esta página.


Total 14 Páginas

No Preview Available ! NCP5214 Hoja de datos, Descripción, Manual

www.DataSheet4U.com
NCP5214
Product Preview
2−in−1 Notebook DDR
Power Controller
The NCP5214 2−in−1 Notebook DDR Power Controller is
specifically designed as a total power solution for notebook DDR
memory system. This IC combines the efficiency of a PWM
controller for the VDDQ supply with the simplicity of linear
regulators for the VTT termination voltage and the buffered low
noise reference. This IC contains a synchronous PWM buck
controller for driving two external NFETs to form the DDR memory
supply voltage (VDDQ). The DDR memory termination regulator
output voltage (VTT) and the buffered VREF are internally set to
track at the half of VDDQ. An internal power good voltage monitor
tracks VDDQ output and notifies the user whether the VDDQ output
is within target range. Protective features include soft−start
circuitries, undervoltage monitoring of supply voltage, VDDQ
overcurrent protection, VDDQ overvoltage and undervoltage
protections, and thermal shutdown. The IC is packaged in DFN−22.
Features
Incorporates VDDQ, VTT Regulator, Buffered VREF
Adjustable VDDQ Output
VTT and VREF Track VDDQ/2
Operates from Single 5.0 V Supply
Supports VDDQ Conversion Rails from 5.0 V to 24 V
Power−saving Mode for High Efficiency at Light Load
Integrated Power FETs with VTT Regulator Sourcing/Sinking 1.5 A
DC and 2.4 A Peak Current
Buffered Low Noise 15 mA VREF Output
All External Power MOSFETs are N−channel
<5.0 mA Current Consumption During Shutdown
Fixed Switching Frequency of 400 kHz
Soft−start Protection for VDDQ and VTT
Undervoltage Monitor of Supply Voltage
Overvoltage Protection and Undervoltage Protection for VDDQ
Short−circuit Protection for VDDQ and VTT
Thermal Shutdown
Housed in DFN−22
Typical Applications
Notebook DDR/DDR2 Memory Supply and Termination Voltage
Active Termination Busses (SSTL−18, SSTL−2, SSTL−3)
http://onsemi.com
MARKING
DIAGRAM
1
22 DFN−22
MN SUFFIX
NCP5214
CASE 506AF
AWLYYWW
1
NCP5214 = Specific Device Code
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
PIN CONNECTIONS
VDDQEN
VTTEN
FPWM
SS
VTTGND
VTT
VTTI
FBVTT
AGND
DDQREF
VCCA
PGND
BGDDQ
VCCP
SWDDQ
TGDDQ
BOOST
OCDDQ
PGOOD
VTTREF
FBDDQ
COMP
(Top View)
NOTE: Pin 23 is the thermal pad on
the bottom of the device.
ORDERING INFORMATION
Device
Package
Shipping
NCP5214MNR2 DFN−22 2500 Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
© Semiconductor Components Industries, LLC, 2005
April, 2005 − Rev. P0
1
Publication Order Number:
NCP5214/D

1 page




NCP5214 pdf
NCP5214
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Power Supply Voltage (Pin 11, 20) to AGND (Pin 9)
High−Side Gate Drive Supply: BOOST (Pin 17) to SWDDQ (Pin 19)
High−Side FET Gate Drive Voltage: TGDDQ (Pin 18) to SWDDQ (Pin 19)
Input/Output Pins to AGND (Pin 9)
Pins 1−4, 6−8, 10, 12−15, 21
VCCA, VCCP
VBOOST−VSWDDQ,
VTGDDQ−VSWDDQ
VIO
−0.3, 6.0
−0.3, 6.0
−0.3, 6.0
V
V
V
Overcurrent Sense Input (Pin 16) to AGND (Pin 9)
Switch Node (Pin 19)
VOCDDQ
VSWDDQ
27
−4.0 (<100 ns),
0.3 (dc), 32
V
V
PGND (Pin 22), VTTGND (Pin 5) to AGND (Pin 9)
Thermal Characteristics
DFN−22 Plastic Package
Thermal Resistance, Junction−to−Ambient
VGND
RqJA
−0.3, 0.3
35
V
_C/W
Operating Junction Temperature Range
TJ
0 to +150
_C
Operating Ambient Temperature Range
TA
−40 to +85
_C
Storage Temperature Range
Tstg
−55 to +150
_C
Moisture Sensitivity Level
MSL
2−
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values
(not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage
may occur and reliability may be affected.
1. This device series contains ESD protection and exceeds the following tests:
Human Body Model (HBM) 2.0 kV per JEDEC standard: JESD22–A114.
Machine Model (MM) 200 V per JEDEC standard: JESD22–A115.
2. Latchup Current Maximum Rating: 150 mA per JEDEC standard: JESD78.
http://onsemi.com
5

5 Page





NCP5214 arduino
NCP5214
APPLICATION INFORMATION
Overcurrent Protection
The OCP circuit is configured to set the current limit for
the current flowing through the high−side FET and
inductor during S0 and S3. The overcurrent tripping level
is programmed by an external resistor RL1 connected
between the OCDDQ pin and drain of the high−side FET.
An internal 35 mA current sink (IOC) at pin OCDDQ
establishes a voltage drop across the resistor RL1 at a
magnitude of RL1xIOC. Besides, an additional offset
voltage VOFFSET of 25 mV is developed at the
non−inverting input of the current limit comparator. The
voltage at the non−inverting input is then compared to the
voltage at SWDDQ pin when the high−side gate drive is
high after a fixed period of blanking time (150 ns) to avoid
false current limit triggering. When the voltage at SWDDQ
is lower than the voltage at the non−inverting input of the
current limit comparator for a consecutive 15 internal clock
cycles, an overcurrent condition occurs, during which, all
outputs will be latched off to protect against a
short−to−ground condition on SWDDQ or VDDQ. i.e., the
voltage drop across the Rds(on) of high−side FET developed
by the drain current is larger than the voltage drop across
RL1 plus the additional offset voltage, the OCP is triggered
and the device will be latched off.
The overcurrent protection will trip when a peak inductor
current hit the ILIMIT determined by the equation:
ILIMIT + RL1
IOC ) VOFFSET
Rds(on)
Since the MOSFET Rds(on) varies with temperature as
current flows through the MOSFET increases, the OCP trip
point will also varies with the MOSFET Rds(on)
temperature variation. The IOC temperature coefficient of
3200 ppm is used to compensate the Rds(on) temperature
variation.
To avoid false triggering the overcurrent protection in
normal operating load range, calculate the RL1 value from
the above equation with the following condition:
1. The minimum IOC value from the specification
table,
2. The maximum Rds(on) of the MOSFET used at
the highest junction temperature,
3. Determine ILIMIT for ILIMIT > IOUT(MAX) + DIL/2.
Besides, a decoupling capacitor CDCPL should be added
closed to the lead of the current limit setting resistor RL1
which connected to the drain of the high−side MOSFET.
Soft−Start
A VDDQ soft−start feature is incorporated in the device
to prevent surge current from power supply and output
voltage overshot during power up. When VDDQEN,
VCCA, and VOCDDQ rise above their respective upper
threshold voltages, the external soft−start capacitor Css
will be charged up by a constant current source, Iss. When
the soft−start voltage (Vcss) rises above the SS_EN voltage
(X50 mV), the BGDDQ and TGDDQ will start switching
and VDDQ output will ramp up. When the soft−start
voltage reaches the SS_OK voltage (XVref + 50 mV), the
soft− start of VDDQ is finished. The Css will continue to
charge up until it reaches about 2.5 V to 3.0 V.
The soft−start time tss can be programmed according to
the following equation:
tss
[
0.8
Css
Iss
Ceramic capacitors with low tolerance and low
temperature coefficient, such as B, X5R, X7R ceramic
capacitors are recommended to be used as the Css. Ceramic
capacitors with Y5V temperature characteristic are not
recommended.
http://onsemi.com
11

11 Page







PáginasTotal 14 Páginas
PDF Descargar[ Datasheet NCP5214.PDF ]




Hoja de datos destacado

Número de piezaDescripciónFabricantes
NCP5210PWM Dual Buck and Linear DDR Power ControllerON Semiconductor
ON Semiconductor
NCP5211Low Voltage Synchronous Buck ControllerON Semiconductor
ON Semiconductor
NCP5211ALow Voltage Synchronous Buck ControllerON Semiconductor
ON Semiconductor
NCP5212ASingle Synchronous Step-Down ControllerON Semiconductor
ON Semiconductor

Número de piezaDescripciónFabricantes
SLA6805M

High Voltage 3 phase Motor Driver IC.

Sanken
Sanken
SDC1742

12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.

Analog Devices
Analog Devices


DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.


DataSheet.es    |   2020   |  Privacy Policy  |  Contacto  |  Buscar