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PDF DP83848H Data sheet ( Hoja de datos )
| Número de pieza | DP83848H | |
| Descripción | Extreme Temperature Single 10/100 Ethernet Transceiver | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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www.DataSheet4U.com
September 2006
DP83848H PHYTER® Mini - Extreme Temperature
Single 10/100 Ethernet Transceiver
General Description
Features
The DP83848H PHYTER® Mini Extreme addresses the • Low-power 3.3V, 0.18µm CMOS technology
high quality, high reliability and small form factor required • 3.3V MAC Interface
for rugged operation in space sensitive and thermally
demanding environments. This device is ideally suited for
•
Auto-MDIX for 10/100 Mb/s
industrial and motor control, building/factory automation, • Energy Detection Mode
automotive and test equipment applications.
• MII Interface and MII serial management interface (MDC
The DP83848H is designed from ground up for extreme and MDIO)
temperature performance, with a thermally efficient pack- • IEEE 802.3u Auto-Negotiation and Parallel Detection
age ensuring reliable operation over an operating range of • IEEE 802.3u ENDEC, 10BASE-T transceivers and filters
-40C to 125C. Rigorously tested at both low temperature • IEEE 802.3u PCS, 100BASE-TX transceivers and filters
and high temperature extremes, the device is ideal for out-
door environments and demanding factory floor conditions. • Integrated ANSI X3.263 compliant TP-PMD physical sub-
layer with adaptive equalization and Baseline Wander
The device offers performance beyond the IEEE specifica- compensation
tions, with superior interoperability and industry leading
performance. The DP83848H offers Auto-MDIX to remove
•
Error-free Operation up to 137 meters
cabling complications, superior ESD protection of greater • ESD protection - 4KV Human body model
than 4KV HBM for greater reliability, and superior cable • LED support for Link
length operation (greater than 137m) to provide a high
level of performance in all applications.
•
Supports system clock from oscillator
• Single register access for complete PHY status
A number of system cost-reducing features have been
integrated that are not commonly found in other Ethernet
•
10/100 Mb/s packet BIST (Built in Self Test)
Physical layer products (PHYs). For example, the • 40 pin LLP package (6mm) x (6mm) x (0.8mm)
DP83848H offers a 25MHz clock out that eliminates the
need and hence the space and cost, of an additional Applications
Media Access Control (MAC) clock source component.
• Peripheral devices
DP83848H is offered in a small 6mm x 6mm LLP 40-pin • Mobile devices
package.
• Factory and building automation
• Basestations
System Diagram
MPU/CPU
MII
DP83848H
10/100 Ethernet
Transceiver
Clock
Source
Status
LED
Typical Ethernet Application
PHYTER® is a registered trademark of National Semiconductor Corporation.
© 2006 National Semiconductor Corporation
10BASE-T
or
100BASE-TX
www.national.com
1 page  
8.2.14 10BASE-T Transmit Timing (End of Packet) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
8.2.15 10BASE-T Receive Timing (Start of Packet) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
8.2.16 10BASE-T Receive Timing (End of Packet) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
8.2.17 10 Mb/s Heartbeat Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
8.2.18 10 Mb/s Jabber Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
8.2.19 10BASE-T Normal Link Pulse Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
8.2.20 Auto-Negotiation Fast Link Pulse (FLP) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
8.2.21 100BASE-TX Signal Detect Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
8.2.22 100 Mb/s Internal Loopback Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
8.2.23 10 Mb/s Internal Loopback Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
8.2.24 Isolation Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
8.2.25 25 MHz_OUT Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
5 www.national.com
5 Page 
1.6 Strap Options
DP83848H uses many functional pins as strap options.
The values of these pins are sampled during reset and
used to strap the device into specific modes of operation.
The strap option pin assignments are defined below. The
functional pin name is indicated in parentheses.
A 2.2 kΩ resistor should be used for pull-down or pull-up to
change the default strap option. If the default option is
required, then there is no need for external pull-up or pull
down resistors. Since these pins may have alternate func-
tions after reset is deasserted, they should not be con-
nected directly to VCC or GND.
Signal Name
PHYAD0 (COL)
PHYAD1 (RXD_0)
PHYAD2 (RXD_1)
PHYAD3 (RXD_2)
PHYAD4 (RXD_3)
AN0 (LED_LINK)
LED_CFG (CRS)
MDIX_EN (RX_ER)
Type
S, O, PU
S, O, PD
S, O, PU
Pin #
35
36
37
38
39
22
Description
PHY ADDRESS [4:0]: The DP83848H provides five PHY ad-
dress pins, the state of which are latched into the PHYCTRL reg-
ister at system Hardware-Reset.
The DP83848H supports PHY Address strapping values 0
(<00000>) through 31 (<11111>). A PHY Address of 0 puts the
part into the MII Isolate Mode. The MII isolate mode must be se-
lected by strapping Phy Address 0; changing to Address 0 by reg-
ister write will not put the Phy in the MII isolate mode. Please refer
to section 2.3 for additional information.
PHYAD0 pin has weak internal pull-up resistor.
PHYAD[4:1] pins have weak internal pull-down resistors.
This input pin controls the advertised operating mode of the
DP83848H according to the following table. The value on this pin
is set by connecting it to GND (0) or VCC (1) through 2.2 kΩ resis-
tors. This pin should NEVER be connected directly to GND or
VCC.
The value set at this input is latched into the DP83848H at Hard-
ware-Reset.
The float/pull-down status of this pin is latched into the Basic
Mode Control Register and the Auto_Negotiation Advertisement
Register during Hardware-Reset.
The default is 1 since this pin has an internal pull-up.
S, O, PU
S, O, PU
AN0
Advertised Mode
0 10BASE-T Half-Duplex
100BASE-TX, Half-Duplex
1 10BASE-T, Half/Full-Duplex
100BASE-TX, Half/Full-Duplex
33 LED CONFIGURATION: This strapping option determines the
mode of operation of the LED pins. Default is Mode 1. Mode 1 and
Mode 2 can be controlled via the strap option. All modes are con-
figurable via register access.
SeeTable 3 for LED Mode Selection.
34 MDIX ENABLE: Default is to enable MDIX. This strapping option
disables Auto-MDIX. An external pull-down will disable Auto-
MDIX mode.
11 www.national.com
11 Page | ||
| Páginas | Total 70 Páginas | |
| PDF Descargar | [ Datasheet DP83848H.PDF ] | |
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