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PDF AD5666 Datasheet ( Hoja de datos )

Número de pieza AD5666
Descripción 16-Bit DAC
Fabricantes Analog Devices 
Logotipo Analog Devices Logotipo
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AD5666 datasheet

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AD5666 pdf
AD5666
VDD = 2.7 V to 3.6 V, RL = 2 kΩ to GND, CL = 200 pF to GND, VREFIN = VDD. All specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
STATIC PERFORMANCE2
Resolution
Relative Accuracy
Differential Nonlinearity
Zero-Code Error
Zero-Code Error Drift
Full-Scale Error
Gain Error
Gain Temperature
Coefficient
Offset Error
DC Power Supply Rejection
Ratio
DC Crosstalk
(External Reference)
DC Crosstalk
(Internal Reference)
OUTPUT CHARACTERISTICS3
Output Voltage Range
Capacitive Load Stability
DC Output Impedance
Short-Circuit Current
Power-Up Time
REFERENCE INPUTS
Reference Input Voltage
Reference Current
Reference Input Range
Reference Input Impedance
REFERENCE OUTPUT
Output Voltage
Reference TC3
Reference Output
Impedance
LOGIC INPUTS3
Input Current
Input Low Voltage, VINL
Input High Voltage, VINH
Pin Capacitance
LOGIC OUTPUTS (SDO)3
Output Low Voltage, VOL
Output High Voltage, VOH
High Impedance Leakage
Current
High Impedance Leakage
Current
A Grade1
Min Typ Max
16
±32
±1
19
±2
−0.2 −1
±1
±2.5
±1 ±9
–80
10
5
10
25
10
0 VDD
2
10
0.5
30
4
VDD
40 50
0 VDD
14.6
1.247
±5
7.5
1.253
±15
2
3
VDD
0.5
2
±3
0.8
0.4
±0.25
B Grade1
Min Typ Max
16
±16
±1
19
±2
−0.2 −1
±1
±2.5
±1 ±9
–80
10
5
10
25
10
0 VDD
2
10
0.5
30
4
VDD
40 50
0 VDD
14.6
1.247
±5
7.5
1.253
±15
2
3
VDD
0.5
2
±3
0.8
0.4
±0.25
Unit
Bits
LSB
LSB
mV
μV/°C
% FSR
% FSR
ppm
mV
dB
μV
μV/mA
μV
μV
μV/mA
V
nF
nF
Ω
mA
μs
V
μA
V
ppm/°C
μA
V
V
pF
V
μA
pF
Conditions/Comments
See Figure 5
Guaranteed monotonic by design (see Figure 6)
All 0s loaded to DAC register (see Figure 13)
All 1s loaded to DAC register (see Figure 12)
Of FSR/°C
VDD ± 10%
Due to full-scale output change,
RL = 2 kΩ to GND or VDD
Due to load current change
Due to powering down (per channel)
Due to full-scale output change,
RL = 2 kΩ to GND or VDD
Due to load current change
RL = ∞
RL = 2 kΩ
VDD = 3 V coming out of power-down mode
Coming out of power-down VDD = 3 V
VREF = VDD = 3.6 V
Per DAC channel
At ambient
VDD = 3 V
VDD = 3 V
ISINK = 2 mA
ISOURCE = 2 mA
Rev. A | Page 5 of 28

5 Page

AD5666 arduino
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
LDAC 1
SYNC 2
VDD 3
VOUTA 4
VOUTC 5
POR 6
VREFIN/VREFOUT 7
AD5666
TOP VIEW
(Not to Scale)
14 SCLK
13 DIN
12 GND
11 VOUTB
10 VOUTD
9 CLR
8 SDO
Figure 5. 14-Lead TSSOP (RU-14)
AD5666
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Description
1 LDAC
2 SYNC
Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data.
This allows all DAC outputs to simultaneously update. Alternatively, this pin can be tied permanently low.
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes
low, it powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in
on the falling edges of the next 32 clocks. If SYNC is taken high before the 32nd falling edge, the rising
edge of SYNC acts as an interrupt and the write sequence is ignored by the device.
3 VDD
Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should be decoupled
with a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND.
4 VOUTA
Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
5 VOUTC
Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
6 POR
Power-on Reset Pin. Tying this pin to GND powers up the part to 0 V. Tying this pin to VDD powers up
the part to midscale.
7
VREFIN/VREFOUT
The AD5666 has a common pin for reference input and reference output. When using the internal
reference, this is the reference output pin. When using an external reference, this is the reference input
pin. The default for this pin is as a reference input.
8 SDO
Serial Data Output. Can be used for daisy-chaining a number of these devices together or for reading
back the data in the shift register for diagnostic purposes. The serial data is transferred on the rising edge
of SCLK and is valid on the falling edge of the clock.
9 CLR
Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are
ignored. When CLR is activated, the input register and the DAC register are updated with the data
contained in the CLR code register—zero, midscale, or full scale. Default setting clears the output to 0 V.
10 VOUTD
11 VOUTB
12 GND
13 DIN
14 SCLK
Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
Ground Reference Point for All Circuitry on the Part.
Serial Data Input. This device has a 32-bit shift register. Data is clocked into the register on the falling
edge of the serial clock input.
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input.
Data can be transferred at rates of up to 50 MHz.
Rev. A | Page 11 of 28

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