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PDF AD5664 Datasheet ( Hoja de datos )

(AD5624 / AD5664) nanoDACs - Analog Devices

Número de pieza AD5664
Descripción (AD5624 / AD5664) nanoDACs
Fabricantes Analog Devices 
Logotipo Analog Devices Logotipo
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AD5664 datasheet

1 Page

AD5664 pdf
AD5624/AD5664
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2 (see Figure 2).
VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 4.
Parameter1
t1 2
t2
t3
t4
t5
t6
t7
t8
t9
t10
Limit at TMIN, TMAX
VDD = 2.7 V to 5.5 V
20
9
9
13
5
5
0
15
13
0
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Conditions/Comments
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK falling edge setup time
Data setup time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
SYNC rising edge to SCLK fall ignore
SCLK falling edge to SYNC fall ignore
1 Guaranteed by design and characterization, not production tested.
2 Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V.
TIMING DIAGRAM
SCLK
SYNC
DIN
t10
t8
t4
DB23
t6
t5
t1
t3 t2
t9
t7
DB0
Figure 2. Serial Write Operation
Rev. 0 | Page 5 of 24

5 Page

AD5664 arduino
AD5624/AD5664
8 VDD = 3.6V
TA = 25°C
7
6
5
4
3
2
1
0
0.39
0.40
0.41
0.42
0.43
IDD (mA)
Figure 16. IDD Histogram with VDD = 3.6 V
0.20
0.15
VDD = VREF = 5V, 3V
TA = 25°C
0.10
DAC LOADED WITH
ZERO SCALE –
SINKING CURRENT
0.05
0
–0.05
–0.10
–0.15
DAC LOADED WITH
–0.20
FULL SCALE –
SOURCING CURRENT
–0.25
–5 –4 –3 –2 –1 0 1 2 3 4 5
I (mA)
Figure 17. Headroom at Rails vs. Source and Sink Current
0.50
0.45
VDD = VREFIN = 5V
0.40
0.35
VDD = VREFIN = 3V
0.30
0.25
0.20
0.15
0.10
0.05
TA = 25°C
0
–40 –20
0 20 40 60
TEMPERATURE (°C)
80 100
Figure 18. Supply Current vs. Temperature
VDD = VREF = 5V
TA = 25°C
FULL-SCALE CODE CHANGE
0x0000 TO 0xFFFF
OUTPUT LOADED WITH 2k
AND 200pF TO GND
VOUT = 909mV/DIV
1
TIME BASE = 4µs/DIV
Figure 19. Full-Scale Settling Time, 5 V
VDD = VREF = 5V
TA = 25°C
VDD
1
2
VOUT
CH1 2.0V CH2 500mV
MAX(C2)
420.0mV
M100µs 125MS/s 8.0ns/pt
A CH1 1.28V
Figure 20. Power-On Reset to 0 V
SYNC
1
SLCK
3
VOUT
VDD = 5V
2
CH1 5.0V
CH3 5.0V
CH2 500mV
M400ns
A CH1
Figure 21. Exiting Power-Down to Midscale
1.4V
Rev. 0 | Page 10 of 24

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