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PDF ZL50053 Data sheet ( Hoja de datos )
| Número de pieza | ZL50053 | |
| Descripción | (ZL50051 / ZL50053) 8 K Channel Digital Switch | |
| Fabricantes | Zarlink Semiconductor | |
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ZL50051/3
8 K Channel Digital Switch with High Jitter
Tolerance, Single Rate (8 or 16 Mbps),
and 64 Inputs and 64 Outputs
Data Sheet
Features
• 8,192 channel x 8,192 channel non-blocking
unidirectional switching. The Backplane and
Local inputs and outputs can be combined to form
a non-blocking switching matrix with 64 input
streams and 64 output streams
• 4,096 channel x 4,096 channel non-blocking
Backplane input to Local output stream switch
• 4,096 channel x 4,096 channel non-blocking
Local input to Backplane output stream switch
• 4,096 channel x 4,096 channel non-blocking
Backplane input to Backplane output switch
• 4,096 channel x 4,096 channel non-blocking
Local input to Local output stream switch
• Backplane port accepts 32 input and 32 output
ST-BUS streams with a fixed data rate of
8.192 Mbps, or 16 input and 16 output ST-BUS
streams with a fixed data rate of 16.384 Mbps
• Local port accepts 32 input and 32 output ST-
BUS streams with a fixed data rate of
8.192 Mbps, or 16 input and 16 output ST-BUS
streams with a fixed data rate of 16.384 Mbps
• Exceptional input clock jitter tolerance (17 ns)
December 2003
Ordering Information
ZL50051GAC 256 ball PBGA
ZL50053QCC 256 pin LQFP
-40°C to +85°C
• Per-stream bit delay for Local and Backplane
input streams
• Per-stream advancement for Local and Backplane
output streams
• Constant 2-frame throughput delay for frame
integrity
• Per-channel high impedance output control for
Local and Backplane streams
• Per-channel driven-high output control for Local
and Backplane streams
• Per-channel message mode for Local and
Backplane output streams
• Connection memory block programming for fast
device initialization
VDD_IO VDD_CORE
VSS (GND)
RESET
ODE
BSTi0-31
Backplane Data Memories
(4,096 channels)
Local
Interface
LSTi0-31
BSTo0-31
Backplane
Interface
Backplane
Connection Memory
(4,096 locations)
Local
Connection Memory
(4,096 locations)
Local
Interface
LSTo0-31
BORS
FP8i
C8i
Input
Timing Unit
PLL
Local Data Memories
(4,096 channels)
Microprocessor Interface
and Internal Registers
Output
Timing
Unit
Test Port
LORS
FP8o
FP16o
C8o
C16o
VDD_PLL
DS CS R/W A14-0 DTA D15-0 TMS TDi TDo TCK TRST
Figure 1 - ZL50051/3 Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003, Zarlink Semiconductor Inc. All Rights Reserved.
1 page  
ZL50051/3
Data Sheet
Table of Contents
13.1 Control Register (CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
13.2 Block Programming Register (BPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
13.3 Local Input Bit Delay Registers (LIDR0 to LIDR31). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
13.3.1 Local Input Delay Bits 4-0 (LID[4:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
13.4 Backplane Input Bit Delay Registers (BIDR0 to BIDR31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
13.4.1 Backplane Input Delay Bits 4-0 (BID[4:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
13.5 Local Output Advancement Registers (LOAR0 to LOAR31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
13.5.1 Local Output Advancement Bits 1-0 (LOA1-LOA0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
13.6 Backplane Output Advancement Registers (BOAR0 - BOAR31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
13.6.1 Backplane Output Advancement Bits 1-0 (BOA1-BOA0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
13.7 Memory BIST Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
13.8 Bit Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
13.9 Device Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
14.0 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
15.0 AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5
Zarlink Semiconductor Inc.
5 Page 
ZL50051/3
Data Sheet
Pin Description (continued)
Pin Name
ZL50053
Package
Coordinates
(256 pin
LQFP)
ZL50051
Package
Coordinates
(256 ball
PBGA)
Description
FP16o
NA
P11 Frame Pulse Output (5 V Tolerant Three-state Output)
When the Frame Pulse Width bit (FPW) of the Control
Register is LOW (default), this pin outputs a 61 ns-wide frame
pulse. When the FPW bit is HIGH, this pin outputs a
122 ns-wide frame pulse. The frame pulse, running at 8 kHz
rate, will have the same format (ST-BUS or GCI-Bus) as the
input frame pulse (FP8i). Output data on both the Backplane
and Local sides (BSTo0-31 and LSTo0-31) will be aligned to
this frame pulse and the accompanying output clock, C16o.
Backplane and Local Inputs
BSTi0-15
228, 229,
230, 231,
232, 233,
234, 235,
236, 238,
237, 240,
239, 242,
241, 244
K1, K2, K3,
K4, L1, L2,
L3, L4, M1,
M2, M3, M4,
N1, N2, N3,
N4
Backplane Serial Input Streams 0 to 15 (5 V Tolerant Inputs with
Internal Pull-downs)
These pins accept serial TDM data streams at a data rate of:
16.384 Mbps (with 256 channels per stream), or 8.192 Mbps
(with 128 channels per stream).
BSTi16-31
248, 250,
249, 252,
251, 254,
253, 255,
256, 1, 2, 3,
4, 6, 5, 8
N5, P1, P2,
P3, P4, P5,
R1, R2, R3,
R4, R5, T1,
T2, T3, T4, T5
Backplane Serial Input Streams 16 to 31 (5 V Tolerant Inputs with
Internal Pull-downs)
These pins accept serial TDM data streams at a data rate of:
8.192 Mbps (with 128 channels per stream).
When the device operates at 16.384 Mbps, these pins are
unused and should be externally connected to a defined logic
level.
LSTi0-15
83, 81, 82,
79, 80, 77,
78, 75, 76,
73, 74, 71,
72, 66, 65, 64
K13, K14,
K15, K16,
L13, L14,
L15, L16,
M13, M14,
M15, M16,
N12, N13,
N14, N15
Local Serial Input Streams 0 to 15 (5 V Tolerant Inputs with
Internal Pull-downs)
These pins accept serial TDM data streams at a data rate of:
16.384 Mbps (with 256 channels per stream), or 8.192 Mbps
(with 128 channels per stream).
LSTi16-31
63, 62, 61,
59, 60, 57,
58, 55, 56,
53, 54, 51,
52, 46, 45, 44
N16, P12,
P13, P14,
P15, P16,
R12, R13,
R14, R15,
R16, T12,
T13, T14,
T15, T16
Local Serial Input Streams 16 to 31 (5 V Tolerant Inputs with
Internal Pull-downs)
These pins accept serial TDM data streams at a data rate of:
8.192 Mbps (with 128 channels per stream).
When the device operates at 16.384 Mbps, these pins are
unused and should be externally connected to a defined logic
level.
11
Zarlink Semiconductor Inc.
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ZL50053.PDF ] | |
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