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PDF ZL50031 Data sheet ( Hoja de datos )
| Número de pieza | ZL50031 | |
| Descripción | Flexible 4 K x 2 K Channel Digital Switch | |
| Fabricantes | Zarlink Semiconductor | |
| Logotipo |  |
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ZL50031
Flexible 4 K x 2 K Channel Digital Switch
with H.110 Interface and
2 K x 2 K Local Switch
Data Sheet
Features
• 4,096 x 2,048 blocking switching between
backplane and local streams
• 2,048 x 2,048 non-blocking switching between
local streams
• 2,048 x 2,048 non-blocking switching between
backplane streams
• Rate conversion between backplane and local
streams
• Backplane interface accepts data rates of
8.192 Mbps or 16.384 Mbps
• Local interface accepts data rates of 2.048 Mbps,
4.096 Mbps or 8.192 Mbps on a per group basis
• Meets all the key H.110 mandatory signal
requirements including timing
• Per-channel variable or constant throughput
delay
• Per-stream input delay, programmable for local
streams on a per bit basis
• Per-stream output advancement, programmable
for backplane and local streams
• Per-channel direction control for backplane
streams
• Per-channel message mode for backplane and
local streams
• Per-channel high impedance output control for
backplane and local streams
• Compatible to Stratum 4 Enhanced clock
switching standard
• Integrated PLL conforms to Telcordia GR-1244-
CORE Stratum 4 Enhanced switching standard
- Holdover Mode with holdover frequency stability
of 0.07 ppm
- Jitter attenuation from 1.52 Hz
- Time interval error (TIE) correction
- Master and Slave mode operation
• Non-multiplexed microprocessor interface
February 2005
Ordering Information
ZL50031QEG1 256 Pin HQFP*
*Pb Free Matte Tin
-40°C to +85°C
• Connection memory block-programming for fast
device initialization
• Pseudo-Random Binary Sequence (PRBS) pattern
generation and testing for backplane and local
streams
• Conforms to the mandatory requirements of the
IEEE-1149.1 (JTAG) standard
• 3.3 V operation with 5 V tolerant inputs and I/O’s
• 5 V tolerant PCI driver on CT-Bus I/O’s
Applications
• Carrier-grade VoIP Gateways
• IP-PBX and PABX
• Intregrated Access Devices
• Access Servers
• CTI Applications/CompactPCI® Platforms
• H.110, H.100, ST-BUS and proprietary Backplane
Applications
Description
The ZL50031 Digital Switch provides switching
capacities of 4,096 x 2,048 channels between
backplane and local streams, 2,048 x 2,048 channels
among local streams and 2,048 x 2,048 channels
among backplane streams. The local connected serial
inputs and outputs have 32, 64 and 128 64 kbps
channels per frame with data rates of 2.048, 4.096 and
8.192 Mbps respectively. The backplane connected
serial inputs and outputs have 128 and 256 64 kbps
channels per frame with data rates of 8.192 and
16.384 Mbps respectively.
Zarlink Semiconductor US Patent No. 5,602,884, UK Patent No. 0772912,
France Brevete S.G.D.G. 0772912; Germany DBP No. 69502724.7-08
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2005, Zarlink Semiconductor Inc. All Rights Reserved.
1 page  
ZL50031
Data Sheet
List of Figures
Figure 1 - Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Figure 1 - ZL50031 256-Pin 28 mm x 28 mm HQFP (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 2 - CT-Bus Timing for 8 Mbps Backplane Data Streams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 3 - ST-BUS Timing for 16 Mbps Backplane Data Streams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 4 - Block Programming Data in the Connection Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 5 - Typical Timing Control Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 6 - DPLL Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 7 - State Machine Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 8 - Block Diagram of the PLL Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 9 - Skew Control Circuit Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 10 - DPLL Jitter Transfer Function Diagram - Wide Range of Frequencies . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 11 - Detailed DPLL Jitter Transfer Function Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 12 - Local Input Bit Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 13 - Example of Backplane Output Advancement Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 14 - Local Output Advancement Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 15 - Backplane Frame Pulse Input and Clock Input Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 16 - Backplane Frame Pulse Output and Clock Output Timing Diagram (in Primary Master Mode and
Secondary Master Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 17 - Backplane Frame Pulse Input and Clock Input Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 18 - Reference Input Timing Diagram when the input frequency = 8 kHz . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 19 - Reference Input Timing Diagram when the input frequency = 2.048 MHz . . . . . . . . . . . . . . . . . . . . . 59
Figure 20 - Reference Input Timing Diagram when the input frequency = 1.544 Hz . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 21 - Reference Output Timing Diagram when (DIV1, DIV0) = (0, 0) in DOM2 Register . . . . . . . . . . . . . . . 60
Figure 22 - Reference Output Timing Diagram when (DIV1, DIV0) = (0, 0) in DOM2 Register . . . . . . . . . . . . . . . 60
Figure 23 - Reference Input Timing Diagram when (DIV1, DIV0) = (0, 0) in DOM2 Register . . . . . . . . . . . . . . . . 60
Figure 24 - Reference Output Timing Diagram when (DIV1, DIV0) = (1, 0) in DOM2 Register . . . . . . . . . . . . . . . 60
Figure 25 - Reference Output Timing Diagram when (DIV1, DIV0) = (0, 1) in DOM2 Register . . . . . . . . . . . . . . . 61
Figure 26 - Local Clock Timing Diagram when ST_CKo0/1 frequency = 4.096 MHz . . . . . . . . . . . . . . . . . . . . . . 61
Figure 27 - Local Clock Timing Diagram when ST_CKo0/1 frequency = 8.192 MHz . . . . . . . . . . . . . . . . . . . . . . 62
Figure 28 - Local Clock Timing Diagram when ST_CKo frequency = 16.384 MHz . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 29 - C1M5o Output Clock Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 30 - Backplane Serial Stream Timing when the Data Rate is 8 Mbps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 31 - Backplane Serial Stream Timing when the Data Rate is 16 Mbps. . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 32 - Local Serial Stream Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 33 - Local Serial Stream Input Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 34 - Serial Output and External Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 35 - Serial Output and External Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 36 - Output Driver Enable (ODE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 37 - Motorola Non-Multiplexed Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 38 - JTAG Test Port Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 39 - Reset Pin Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
5
Zarlink Semiconductor Inc.
5 Page 
ZL50031
Data Sheet
Pin Description (continued)
256 Pin HQFP
154
25,38,39,40,47,
50,51,52,53,121,
122,123,124,
126,127,128,129,
130,131,132,133
26,27,28,29,
32,33,34,35,
41,42,
80 to 87,
90 to 93,
118,157,158,165,
166,173,174,
181,182,
189 to196
205,206,213,214,
221,222,227,
228,232
24
20
22
23
21
Name
PCI_OE
IC_GND
IC_OPEN
NC
TDi
TDo
TCK
TRST
TMS
Description
PCI Output Enable (3.3 V Tolerant Input). This active low input is the
control signal used to tristate the BSTio0 - 31 pins during hot-swapping.
During normal operation this signal should be low.
Internal Connection. These pins MUST be connected to ground for
normal operation.
Internal Connection. These pins MUST be left open for normal operation.
No Connection. These pins MUST be left unconnected for normal
operation.
Test Serial Data In (3.3 V Input with Internal pull-up). JTAG serial test
instructions and data are shifted in on this pin. This pin is pulled high by an
internal pull-up when not driven.
Test Serial Data Out (3.3 V Tolerant Tri-state Output). JTAG serial data is
output on this pin on the falling edge of TCK. This pin is held in high
impedance state when JTAG is not enabled.
Test Clock (5 V Tolerant Input). Provides the clock to the JTAG test logic.
This pin should be low when JTAG is not enabled.
Test Reset (3.3 V Input with Internal pull-up). Asynchronosly initializes the
JTAG TAP Controller by putting it in the Test-Logic-Reset state. This pin
should be pulled low to ensure that the ZL50031 is in normal functional
mode.
Test Mode Select (5 V Tolerant Input with Enabled Internal Pull-up):
JTAG signal that controls the state transitions of the TAP controller. This pin
is pulled high by an internal pull-up resistor when it is not driven.
11
Zarlink Semiconductor Inc.
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ZL50031.PDF ] | |
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