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PDF ZL50012 Data sheet ( Hoja de datos )

Número de pieza ZL50012
Descripción Flexible 512-ch Digital Switch
Fabricantes Zarlink Semiconductor 
Logotipo Zarlink Semiconductor Logotipo



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ZL50012
Flexible 512-ch Digital Switch
Data Sheet
Features
• 512 channel x 512 channel non-blocking switch at
2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s operation
• Rate conversion between the ST-BUS inputs and
ST-BUS outputs
• Per-stream ST-BUS input with data rate selection
of 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s
• Per-stream ST-BUS output with data rate
selection of 2.048 Mb/s, 4.096 Mb/s or
8.192 Mb/s; the output data rate can be different
than the input data rate
• Per-stream high impedance control output for
every ST-BUS output with fractional bit
advancement
• Per-stream input channel and input bit delay
programming with fractional bit delay
• Per-stream output channel and output bit delay
programming with fractional bit advancement
• Multiple frame pulse outputs and reference clock
outputs
• Per-channel constant throughput delay
July 2004
Ordering Information
ZL50012/QCC
ZL50012/GDC
160 Pin LQFP
144 Ball LBGA
-40°C to +85°C
• Per-channel high impedance output control
• Per-channel message mode
• Per-channel pseudo random bit sequence
(PRBS) pattern generation and bit error detection
• Control interface compatible to Motorola non-
multiplexed CPUs
• Connection memory block programming
capability
• IEEE-1149.1 (JTAG) test port
• 3.3V I/O with 5 V tolerant input
VDD
VSS
RESET
ODE
STi0-15
S/P Converter
Data Memory
P/S Converter
STo0-15
Output HiZ Control
STOHZ0-15
FPi Connection Memory
CKi Input Timing
FPo0
APLL
Microprocessor
Interface
and
Internal
Registers
Output Timing
CKo0
FPo1
CKo1
FPo2
CKo2
Test Port
IC0 - 4
CLKBYPS
ICONN0 - 2
Figure 1 - ZL50012 Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2002-2004, Zarlink Semiconductor Inc. All Rights Reserved.

1 page




ZL50012 pdf
ZL50012
Data Sheet
List of Tables
Table 1 - FPi and CKi Input Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 2 - FPo0 and CKo0 Output Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 3 - FPo1 and CKo1 Output Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 4 - FPo2 and CKo2 Output Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 5 - Variable Range for Input Streams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 6 - Variable Range for Output Streams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 7 - Data Throughput Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 8 - Connection Memory in Block Programming Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 9 - Definition of the Four Quadrant Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 10 - Quadrant Frame 0 LSB Replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 11 - Quadrant Frame 1 LSB Replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 12 - Quadrant Frame 2 LSB Replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 13 - Quadrant Frame 3 LSB Replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 14 - Address Map for Device Specific Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 15 - Control Register (CR) Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 16 - Internal Mode Selection (IMS) Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 17 - BER Start Receiving Register (BSRR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 18 - BER Length Register (BLR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 19 - BER Count Register (BCR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 20 - Stream Input Control Register 0 to 7 (SICR0 to SICR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 21 - Stream Input Control Register 8 to 15 (SICR8 to SICR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 22 - Stream Input Delay Register 0 to 7 (SIDR0 to SIDR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 23 - Stream Input Delay Register 8 to 15 (SIDR8 to SIDR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 24 - Stream Output Control Register 0 to 7 (SOCR0 to SOCR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 25 - Stream Output Control Register 8 to 15 (SOCR8 to SOCR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 26 - Stream Output Offset Register 0 to 7 (SOOR0 to SOOR7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 27 - Stream Output Offset Register 8 to 15 (SOOR8 to SOOR15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 28 - Address Map for Memory Locations (512 x 512 DX, MSB of address = 1). . . . . . . . . . . . . . . . . . . . . . 51
Table 29 - Connection Memory Bit Assignment when the CMM bit = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 30 - Connection Memory Bits Assignment when the CMM bit = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5
Zarlink Semiconductor Inc.

5 Page





ZL50012 arduino
ZL50012
Data Sheet
Pin Description (continued)
LQFP Pin
Number
115
LBGA Ball
Number
M12
116 H10
117, 118
123 - 125
128 - 130
131 - 134
137 - 139
140 - 142
143, 144
147 - 149
150 - 152
153, 154
M10, M11
L10, L11, K11
K10, L12, K12
J11, J10, J9,
J12
H9, G9, H11
H12, G12, G11
G10, F10
D10, E10, F11
F12, E12, E11
D12, C12
157 D11
158 C11
1, 2, 29,
39 - 42,
79 - 82,
119 - 122,
159, 160
C5, C6
Name
R/W
DS
A0 - A1
A2 - A4
A5 - A7
A8 - A11
STi0 - 2
STi3 - 5
STi6 - 7
STi8 - 10
STi11- 13
STi14 - 15
RESET
TDo
NC
Description
Read/Write (5 V Tolerant Input): This input controls the
direction of the data bus lines (D0-D15) during a
microprocessor access.
Data Strobe (5 V Tolerant Input): This active low input works
in conjunction with CS to enable the microprocessor port read
and write operations.
Address 0 - 11 (5 V Tolerant Inputs): These pins form the 12-
bit address bus to the internal memories and registers.
Serial Input Streams 0 to 15 (5 V Tolerant Inputs): The data
rate of these input streams can be selected independently
using the stream input control registers. In the 2.048 Mb/s
mode, these pins accept serial TDM data streams at
2.048 Mb/s with 32 channels per stream. In the 4.096 Mb/s
mode, these pins accept serial TDM data streams at
4.096 Mb/s with 64 channels per stream. In the 8.192 Mb/s
mode, these pins accept serial TDM data streams at
8.192 Mb/s with 128 channels per stream.
Unused serial input pins are required to connect to either Vdd
or ground, through an external pull-up resistors or external pull-
down resistor.
Device Reset (5 V Tolerant Input): This input (active LOW)
puts the device in its reset state that disables the STo0 - 15
drivers and drives the STOHZ 0 - 15 outputs to high. It also
clears the device registers and internal counters. To ensure
proper reset action, the reset pin must be low for longer than
1 ms. Upon releasing the reset signal to the device, the first
microprocessor access can take place after 600 µs due to the
time required to stabilize the APLL block from the power down
state.
Test Serial Data Out (3 V Tolerant Three-state Output):
JTAG serial data is output on this pin on the falling edge of
TCK. This pin is held in high impedance state when JTAG is not
enabled.
No Connection Pins. These pins are not connected to the
device internally.
14
Zarlink Semiconductor Inc.

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