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PDF PDM41028 Data sheet ( Hoja de datos )

Número de pieza PDM41028
Descripción 1 Megabit Static RAM 256K x 4-Bit
Fabricantes Paradigm 
Logotipo Paradigm Logotipo



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No Preview Available ! PDM41028 Hoja de datos, Descripción, Manual

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Features
n High speed access times
Com’l: 10, 12 and 15 ns
Ind’l: 12 and 15 ns
n Low power operation (typical)
- PDM41028SA
Active: 400 mW
Standby: 150 mW
- PDM41028LA
Active: 350 mW
Standby: 100 mW
n Single +5V (±10%) power supply
n TTL-compatible inputs and outputs
n Packages
Plastic SOJ (300 mil) - TSO
Plastic SOJ (400 mil) - SO
PDM41028
1 Megabit Static RAM
256K x 4-Bit
1
Description
The PDM41028 is a high-performance CMOS static
RAM organized as 262,144 x 4 bits. Writing to this
device is accomplished when the write enable (WE)
and the chip enable (CE) inputs are both LOW.
Reading is accomplished when WE remains HIGH
and CE and OE are both LOW.
2
3
The PDM41028 operates from a single +5V power
supply and all the inputs and outputs are fully TTL-
compatible. The PDM41028 comes in two versions,
the standard power version PDM41028SA and a low
power version the PDM41028LA. The two versions
are functionally the same and only differ in their
power consumption.
The PDM41028 is available in a 28-pin 300-mil SOJ,
and a 28-pin 400-mil SOJ for surface mount
applications.
4
5
6
Functional Block Diagram
Addresses
A0
A17
I/O0
I/O1
I/O2
I/O3
Decoder
Input
Data
Control
Memory
Matrix
•••••
Column I/O
CE
WE
OE
7
8
9
10
11
12
Rev. 2.2 - 4/29/98
1

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PDM41028 pdf
Read Cycle No. 1(4, 5)
ADDR
DOUT
tRC
tAA
tOH
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2(2, 4, 6)
ADDR
CE
OE
DOUT
tAA
tACE
tLZCE
tRC
tLZOE
tAOE
tHZCE
tHZOE
DATA VALID
PDM41028
1
2
3
4
5
6
7
AC Electrical Characteristics
Description
-10(7)
-12(7)
-15
READ Cycle
Sym Min. Max. Min. Max. Min. Max. Units
READ cycle time
tRC 10 12 15 ns
Address access time
tAA 10 12 15 ns
Chip enable access time
tACE
10 12 15 ns
Output hold from address change
tOH 3
3
3
ns
Chip enable to output in low Z(1,3)
tLZCE
5
5
5
ns
Chip disable to output in high Z(1,2,3)
tHZCE
6
6
7 ns
Chip enable to power up time(3)
tPU 0
0
0
ns
Chip disable to power down time(3)
tPD
10 12 15 ns
Output enable access time
tAOE 6 6 6 ns
Output enable to output in low Z (1,3)
tLZOE
0
0
0
ns
Output disable to output in high Z(1,3) tHZOE 6 6 6 ns
SHADED AREA = PRELIMINARY DATA
Notes referenced are after Data Retention Table.
Rev. 2.2 - 4/29/98
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