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| Número de pieza | XCCACEM16 | |
| Descripción | (XCCACEM16 - XCCACEM64) System ACE MPM Solution | |
| Fabricantes | XILINX | |
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System ACE™ MPM Solution
DS087 (v1.2) June 7, 2002
00
Summary
• System level, high capacity, pre-configured solution for
Virtex™ Series FPGAs, Virtex-II Series Platform
FPGAs, and Spartan™ FPGAs
• Industry standard Flash memory die combined with
Xilinx controller technology in a single package
• Effortless density migration:
- XCCACEM16-BG388I (16 Megabit (Mb))
- XCCACEM32-BG388I (32 Mb)
- XCCACEM64-BG388I (64 Mb)
• All densities are available in the 388-pin Ball Grid Array
package
• VCC I/O: 1.8V, 2.5V, and 3.3V
• Configuration rates up to 152 Mb per second (Mb/s)
• Flexible configuration solution:
- SelectMAP (control up to four FPGAs)
- Slave-Serial
- Concurrent Slave-Serial (up to eight separate
chains)
Advance Product Specification
• Patented compression technology (up to 2x
compression)
• JTAG interface allows:
- Access to the standard Flash memory
- Boundary Scan testing
• Native interface to the standard Flash memory is
provided for:
- External parallel programming
- Processor access to unused Flash memory
locations
• Supports up to eight separate design sets (selectable
by mode pins or via JTAG), enabling systems to
reconfigure FPGAs for different functions
• Compatible with IEEE Standard 1532
• User-friendly software to format and program the
bitstreams into the standard Flash via the patented
Flash programming engine
• Internet Reconfigurable Logic (IRL) upgradeable
system
Description
The System ACE Multi-Package Module (MPM) solution
addresses the need for a space-efficient, pre-engineered,
high-density configuration solution in multiple FPGA sys-
tems. The System ACE technology is a ground-breaking
in-system programmable configuration solution that pro-
vides substantial savings in development effort and cost per
bit over traditional PROM and embedded solutions for high
capacity FPGA systems. As shown in Figure 1, the System
ACE MPM solution is a multi-package module that includes
the System ACE MPM controller, a configuration PROM,
and an AMD Flash Memory.
The System ACE MPM has four major interfaces. (See
Figure 2.) The boundary scan JTAG interface is provided for
boundary scan test and boundary-scan-based Flash mem-
ory programming. The system control interface provides an
input for the system clock, design set selection pins, system
configuration control signals, and system configuration sta-
tus signals.
The native Flash memory interface provides direct read and
write access to the Flash memory unit. The target FPGA
interface provides the signals to configure target FPGAs via
the Slave-Serial, concurrent Slave-Serial, or SelectMAP
configuration modes.
Separate power pins provide voltage compatibility control
for the target FPGA configuration interface and for the sys-
tem control/status interface.
See Figure 3 for a complete view of the components and
schematic of the signals in the System ACE MPM.
© 2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS087 (v1.2) June 7, 2002
Advance Product Specification
www.xilinx.com
1-800-255-7778
1
1 page  
R System ACE™ MPM Solution
Table 2: IEEE 1149.1 Boundary Scan Pins
Pin Name
Pin Type
Description
TCK
Input
IEEE 1149.1 test clock pin. The System ACE MPM TCK pin is connected to the
XCV50E and XC18V01 TCK pins. By default, the XCV50E has an internal
pull-up resistor on its TCK pin.
TMS
Input
IEEE 1149.1 test mode select pin. The System ACE MPM TMS pin is
connected to the XCV50E and XC18V01 TMS pins which have internal pull-up
resistors.
TDI
Input
IEEE 1149.1 test data input pin. The System ACE MPM TDI is connected to
the XC18V01 TDI pin which has an internal pull-up resistor.
TDO
Output
IEEE 1149.1 test data output pin. The System ACE MPM TDO pin is connected
to the XCV50E TDO pin which by default has an internal pull-up resistor.
Target FPGA Configuration Pins
Table 3 provides target FPGA configuration pins.
Table 3: Target FPGA Configuration Pins
Pin Name
Pin Type
Description
CFG_DATA[0]
Output
For Slave-Serial configuration mode, CFG_DATA[0] is the serial data signal for
Serial-Slave Chain 0 and is connected to DIN of the first FPGA in the
Slave-Serial Chain 0. For Slave-SelectMAP configuration mode, CFG_DATA[0]
is the data bit 0 on the SelectMAP bus and is connected to D0 on all target
FPGAs.
CFG_DATA[1]
Output
For Slave-Serial configuration mode, CFG_DATA[1] is the serial data signal for
Serial-Slave Chain 1 and is connected to DIN of the first FPGA in the
Slave-Serial Chain 1. For Slave-SelectMAP configuration mode, CFG_DATA[1]
is the data bit 1 on the SelectMAP bus and is connected to D1 on all target
FPGAs.
CFG_DATA[2]
Output
For Slave-Serial configuration mode, CFG_DATA[2] is the serial data signal for
Serial-Slave Chain 2 and is connected to DIN of the first FPGA in the
Slave-Serial Chain 2. For Slave-SelectMAP configuration mode, CFG_DATA[2]
is the data bit 2 on the SelectMAP bus and is connected to D2 on all target
FPGAs.
CFG_DATA[3]
Output
For Slave-Serial configuration mode, CFG_DATA[3] is the serial data signal for
Serial-Slave Chain 3 and is connected to DIN of the first FPGA in the
Slave-Serial Chain 3. For Slave-SelectMAP configuration mode, CFG_DATA[3]
is the data bit 3 on the SelectMAP bus and is connected to D3 on all target
FPGAs.
CFG_DATA[4]
Output
For Slave-Serial configuration mode, CFG_DATA[4] is the serial data signal for
Serial-Slave Chain 4 and is connected to DIN of the first FPGA in the
Slave-Serial Chain 4. For Slave-SelectMAP configuration mode, CFG_DATA[4]
is the data bit 4 on the SelectMAP bus and is connected to D4 on all target
FPGAs.
CFG_DATA[5]
Output
For Slave-Serial configuration mode, CFG_DATA[5] is the serial data signal for
Serial-Slave Chain 5 and is connected to DIN of the first FPGA in the
Slave-Serial Chain 5. For Slave-SelectMAP configuration mode, CFG_DATA[5]
is the data bit 5 on the SelectMAP bus and is connected to D5 on all target
FPGAs.
DS087 (v1.2) June 7, 2002
Advance Product Specification
www.xilinx.com
1-800-255-7778
5
5 Page 
R System ACE™ MPM Solution
Table 6: System ACE MPM Pinout (Continued)
Pin Name
XCCACEM16-BG388I
VCCint2
AA23, AB4, AB23, AC4,
AC11, AC12, AC13, AC18,
AC19, AC20, D17, D18,
D21, D22, D23, E23, H23,
J23, N23, P23, R4, T4, U4,
V26, Y23
GND
A2, A8, A26, AA3, AB24,
AD16, AD22, AE2, AE11,
AE12, AE18, AE22, AE25,
AF1, AF26, B15, B19, B22,
B25, D4, D9, D10, D11,
F23, G4, H25, J4, K23, L4,
L11, L12, L13, L14, L15,
L16, M4, M11, M12, M13,
M14, M15, M16, M23, N11,
N12, N13, N14, N15, N16,
P2, P11, P12, P13, P14,
P15, P16, R1, R11, R12,
R13, R14, R15, R16, R23,
T11, T12, T13, T14, T15,
T16, T23, V25
XCCACEM32-BG388I
AA23, AB4, AB23, AC4,
AC11, AC12, AC13, AC18,
AC19, AC20, D17, D18,
D21, D22, D23, E23, H23,
J23, N23, P23, R4, T4, U4,
V26, Y23
A2, A8, A26, AA3, AB24,
AD16, AD22, AE2, AE11,
AE12, AE18, AE22, AE25,
AF1, AF26, B15, B19, B22,
B25, D4, D9, D10, D11,
F23, G4, H25, J4, K23, L4,
L11, L12, L13, L14, L15,
L16, M4, M11, M12, M13,
M14, M15, M16, M23, N11,
N12, N13, N14, N15, N16,
P2, P11, P12, P13, P14,
P15, P16, R1, R11, R12,
R13, R14, R15, R16, R23,
T11, T12, T13, T14, T15,
T16, T23, V25
XCCACEM64-BG388I
AA23, AB4, AB23, AC4,
AC11, AC12, AC13, AC18,
AC19, AC20, D17, D18,
D21, D22, D23, E23, H23,
J23, N23, P23, R4, T4, U4,
V26, Y23
A2, A8, A26, AA3, AB24,
AD16, AD22, AE2, AE11,
AE12, AE18, AE22, AE25,
AF1, AF26, B15, B19, B22,
B25, D4, D9, D10, D11,
F23, G4, H25, J4, K23, L4,
L11, L12, L13, L14, L15,
L16, M4, M11, M12, M13,
M14, M15, M16, M23, N11,
N12, N13, N14, N15, N16,
P2, P11, P12, P13, P14,
P15, P16, R1, R11, R12,
R13, R14, R15, R16, R23,
T11, T12, T13, T14, T15,
T16, T23, V25
Configuration Overview
The System ACE MPM is engineered for high-speed config-
uration of high-density FPGAs. Multiple configuration
modes are supported to target FPGAs including Concurrent
Slave-Serial mode, Slave-SelectMAP mode, and Slave-Par-
allel mode. The System ACE MPM handles storage of up to
eight separate configuration data sets. Each data set can be
optionally compressed to reduce the overall storage
requirements. One default data set is automatically down-
loaded to the target FPGAs at system power-up. Any one of
the eight data sets can be selected to reconfigure the target
FPGAs at any time during system operation.
Configuration Modes
The System ACE MPM supports high-speed FPGA config-
uration via the Slave-Serial or Slave-SelectMAP configura-
tion modes.
The System ACE MPM solution is a pre-engineered storage
and delivery system with direct support for the high-density
and high-speed configuration needs of the Virtex-II family.
For example, the System ACE MPM can configure a Vir-
tex-II XC2V6000, which requires 19,759,968 configuration
bits, via Slave-Serial mode in 300 milliseconds and via
Slave-SelectMAP mode in 130 milliseconds. In fact, the
System ACE MPM can configure two XC2V6000 devices
concurrently via Slave-Serial mode in 300 milliseconds.See
Table 7 for maximum configuration bit rates. See Table 8 for
FPGA configuration compatibility and cross-reference. See
Table 9 for System ACE MPM and FPGA configuration sig-
nal cross-reference.
DS087 (v1.2) June 7, 2002
Advance Product Specification
www.xilinx.com
1-800-255-7778
11
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| PDF Descargar | [ Datasheet XCCACEM16.PDF ] | |
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