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PDF Z86L7103ZEM Data sheet ( Hoja de datos )
| Número de pieza | Z86L7103ZEM | |
| Descripción | ICEBOX FAMILY IN-CIRCUIT EMULATOR-L71 | |
| Fabricantes | Zilog | |
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CUSTOMER PROCUREMENT SPECIFICATION
1
Z86L7103ZEM
ICEBOX™ FAMILY
IN-CIRCUIT EMULATOR-L71
FEATURES
s Supported Products
Packages
20-Pin PDIP
28-Pin PDIP
40-Pin PDIP
44-Pin PLCC
Emulation
Z86L71/L781
Z86L79/L802
Z86L88/L81/L863
Z86L72/E72/L73/E73/L87/L894
Z86L72/E72/L73/E73/L87/L895
44-Pin QFP
N/A
Notes:
1. Using the supplied 20-pin PDIP L71 Emulation Pod/Cable.
2. Using the supplied 28-pin PDIP L79 Emulation Pod/Cable.
3. Using the supplied 28-pin PDIP L88 Emulation Pod/Cable.
4. Using the supplied 40-pin PDIP L72 Emulation Pod/Cable.
5. Using the supplied 44-pin PLCC L72 Emulation Pod/Cable.
6. Using the supplied OTP Programming Adapter.
OTP Programming
N/A
N/A
N/A
Z86E72/E736
Z86E72/E736
Z86E72/E736
1
s In-Circuit Program Debug Emulation
s Real-Time Emulation
s Z8 GUI Emulator Software
s Window-Based User Interface
s On-Line Help
s One-Time Programmable (OTP) Support
s Selectable Baud Rates – 9600 to 57.6 KB
s Bisync Error-Correcting Communications Protocol
GENERAL DESCRIPTION
Zilog's in-circuit emulators are interactive, Window-orient-
ed development tools, providing a real-time environment
for emulation and debugging.
The Z86L71 Emulator is a member of Zilog's ICEBOX
product family of in-circuit emulators providing support for
the Z86L7X and Z86L8X family of infrared remote control-
lers. The emulator provides essential timing and I/O cir-
cuitry to simplify user emulation of the prototype hardware
and software product.
The Z8L71 Emulator provides users with a hardware plat-
form to develop and debug software in a real-time environ-
ment. In contrast, software simulators provide significantly
slower operation, making them less practical for code de-
velopment.
The Z86L71 Emulator can be connected to a serial port
(COM1, COM2, COM3, and COM4) of the host computer
and uses Graphical User Interface (GUI) software.
CP97LVO2100
1
1 page  
Zilog
8. The general-purpose registers after Power-On Reset
or at initial emulator use will be different than the actual
device. The emulator self-test will always leave the
same values in the general-purpose registers, while
the real device will have a random or undefined value.
9. Power Supply ramp-up/rise time must be such that
when the minimum power-on reset time (Tpor)
expires, the VCC must be in the supported specified
operating range of the device.
10. If Program Counter jumps to an unknown address:
a. Stack is not set to internal. Register %F8 (P01M
Register) bit D2 not set to state “1”.
b. Stack Pointer Register %FE(SPH) and Register
%FF(SPL) are not initialized. For internal Stack,
SPH does not have to be initialized since it is not
used. The SPH and SPL are reset to 00H after any
reset or Stop-Mode Recovery.
c. Any instruction other than “DI” was used to disable
interrupts.
d. The Stack overflowed into the general-purpose
register locations.
e. Extra “POP”, “PUSH”. “IRET”, or “RET” was
encountered.
f. When making changes to the IMR register, the
GLOBAL interrupts must be disabled first using DI
instruction.
11. If the Program keeps resetting:
a. Program Counter rolled over from value “FFFF” to
“0000” and proceeded back to beginning of
program.
b. Watch-Dog Timer (WDT) was not refreshed from
devices with WDT feature.
12. Check the TPOR and TWDT specifications of the device
that you wish to emulate. The actual specification may
differ from the ICE chip specifications. The Z86C50
ICE chip typical WDT time period is configured using
bits 0 and 1 of the WDTMR register located in Bank F
of the Expanded Register Group at address 0FH.
Typical Z86C50 ICE Chip WDT Time-Out Period
Bit 1
0
0
1
1
Internal RC (ms) Time-Out
Bit 0
0
1
0
1
Z86C50
4
9
18
75
In-Circuit Emulator-L71
Note: Typical Z86C50 TPOR = 6.0 ms.
13. Do not start the emulator with OTP device in the
programming socket, as the emulator may not start up
correctly.
14. A shorted PLCC or DIP OTP can crash the emulator
when inserted into the OTP programming socket. If a
PLCC part is inserted in such a way as to cause a
temporary short, then functionality is lost. An attempt
to perform BLANK CHECK on such a part will cause
the “hourglass” to appear continuously. The Windows
application must be reset and restarted.
15. The status color bar in OTP dialog box will be cleared
in the area where a new window opens on top of it.
16. Do not press the emulator MASTER RESET when the
ICEBOX is in the OTP dialog for programming. If
MASTER RESET is pressed while the GUI is doing
OTP programming, close the OTP dialog box and
reopen it to reload the information back to the
hardware.
Note: The ICEBOX is really sitting idle, although the
Command Status shows “Processing” after the GUI
reestablishes the communication link when “Retry”
was selected in the “Out of Synchronization with the
emulator” dialog box.
17. When device serialization is enabled in the OTP
dialog, the GUI copies the current serial number to
code memory immediately before performing a
VERIFY operation. If this behavior is undesirable, then
device serialization should be disabled prior to
invoking the VERIFY operation.
18. The bits of non-implemented features (of devices
having a PCON register) must be set to state “1” on the
emulator.
19. When interrupts are enabled, breakpointing after a
Halt instruction, the emulator will break at the first
instruction in the interrupt service routine that is
serviced when an interrupt occurs.
20. Port 0, Port 1, and Port 2 have auto latches
permanently enabled.
21. SCLK/16 Mode of SMR register is not supported.
22. Programming the ROM protect bit on all Z8 OTPs will
disable all use of the LDC, LDCI, LDE, and LDEI
instructions. Thus, ROM protect does not support the
use of a ROM lookup table. The value must be loaded
as “immediate values”.
The Port 3 Mode Register (R247 P3m) bit D1 must be set
as follows:
1
CP97LVO2100
5
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