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PDF IDT85304-01 Data sheet ( Hoja de datos )
| Número de pieza | IDT85304-01 | |
| Descripción | 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER | |
| Fabricantes | IDT | |
| Logotipo |  |
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IDT85304-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-3.3V
LVPECL FANOUT BUFFER
IDT85304-01
FEATURES:
• Five differential 3.3V LVPECL outputs
• Selectable differential CLK, xCLK, or LVPECL clock inputs
• CLK, xCLK pair can accept the following differential input levels:
LVDS, LVPECL, LVHSTL, SSTL, and HCSL
• PCLK, xPCLK supports the following input types: LVPECL, CML,
and SSTL
• Maximum output frequency: 650MHz
• Translates any single-ended input signal to 3.3V LVPECL levels
with resistor bias on xCLK input
• Output skew: 35ps (max.)
• Part-to-part skew: as low as 150ps
• Propagation delay: 2.1ns (max.)
• 3.3V operating supply
• Available in TSSOP package
DESCRIPTION:
The IDT85304-01 is a low skew, high performance 1-to-5 differential-to-
3.3VLVPECLclockgenerator-divider. Ithastwoselectableclockinputs. The
CLK/xCLKpaircanacceptmoststandarddifferentialinputlevels. ThePCLK/
xPCLKpaircanacceptLVPECL,CML,orSSTLinputlevels. Theclockenable
is internally synchronized to eliminate runt pulses on the outputs during
asynchronous assertion/deassertion of the clock enable pin.
Guaranteedoutputandpart-to-partskewcharacteristicsmaketheIDT85304-
01 ideal for those applications that demand well-defined performance and
repeatability.
FUNCTIONAL BLOCK DIAGRAM
CLK_EN
CLK
xCLK
PCLK
xPCLK
0
1
D
Q
LE
CLK_SEL
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL
c 2004 Integrated Device Technology, Inc.
TEMPERATURE
1
RANGES
Q0
xQ0
Q1
xQ1
Q2
xQ2
Q3
xQ3
Q4
xQ4
MAY 2004
DSC 6174/2
1 page  
IDT85304-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
All parameters measured at 500MHz unless noted otherwise;
Cycle-to-cycle jitter = jitter on output; the part does not add jitter
Symbol
FMAX
tPD
tSK(O)
tSK(PP)
tR
tF
odc
Parameter
Output Frequency
Propagation Delay(1)
Output Skew(2,4)
Part-to-Part Skew(3,4)
Output Rise Time
Output Fall Time
Output Duty Cycle
Test Conditions
f ≤ 650MHz
20 - 80% @ 50MHz
20 - 80% @ 50MHz
Min.
1
300
300
48
Typ. Max. Unit
650 MHz
2.1 ns
35 ps
150 ps
700 ps
700 ps
50 52 %
NOTES:
1. Measured from the differential input crossingpoint to the differential output crossingpoint.
2. Defined as skew between outputs as the same supply voltage and with equal load conditions. Measured at the output differential crosspoints
3. Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each
device, the outputs are measured at the differential crosspoints.
4. This parameter is defined in accordance with JEDEC Standard 65.
5
5 Page 
IDT85304-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL
ORDERING INFORMATION
IDT XXXXX XX X
Device Type Package Process
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
C Commercial (0°C to +70°C)
I Industrial (-40°C to +85°C)
PG Thin Shrink Small Outline Package
85304-01 Low Skew, 1-to-5 Differential-to-3.3V LVPECL
Fanout Buffer
CORPORATE HEADQUARTERS
2975 Stender Way
Santa Clara, CA 95054
for SALES:
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com
11
for Tech Support:
(408) 654-6459
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet IDT85304-01.PDF ] | |
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