PDF ICS87972I Data sheet ( Hoja de datos )

Número de pieza	ICS87972I
Descripción	1-TO-12 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
Fabricantes	ICS
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No Preview Available ! www.DataSheet4U.com Integrated Circuit Systems, Inc. ICS87972I LOW SKEW, 1-TO-12 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER GENERAL DESCRIPTION ,&6 HiPerClockS™ The ICS87972I is a LVCMOS clock generator and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS87972I has three selectable inputs and pro- vides 14 LVCMOS outputs. The ICS87972I is a highly flexible device. Using the crystal os- cillator input, it can be used to generate clocks for a system. All of these clocks can be the same frequency or the device can be configured to generate up to three different frequencies among the three output banks. Using one of the single ended inputs, the ICS87972I can be used as a zero delay buffer/multiplier/divider in clock distribution applications. The three output banks and feedback output each have their own output dividers which allows the device to generate a multitude of different bank frequency ratios and output-to-input frequency ratios. In addition, 2 outputs in Bank C (QC2, QC3) can be selected to be inverting or non-inverting. The output frequency range is 8.33MHz - 125MHz. Input frequency range is 5MHz - 120MHz. FEATURES • Fully integrated PLL • 14 LVCMOS outputs; (12) clocks, (1) feedback, (1) sync • Selectable crystal oscillator interface or LVCMOS reference clock inputs • CLK0, CLK1 can accept the following input levels: LVCMOS or LVTTL • Output frequency range: 8.33MHz to 125MHz • VCO range: 200MHz to 480MHz • Output skew: 550ps (maximum) • Cycle-to-cycle jitter: ±100ps (typical) • Full 3.3V supply voltage • -40°C to 85°C ambient operating temperature • Pin compatible with MPC972 • Compatible with PowerPC™ and Pentium™ Microprocessors The ICS87972I also has a QSYNC output which can be used for system synchronization purposes. It monitors Bank A and Bank C outputs and goes low one period of the faster clock prior to coincident rising edges of Bank A and Bank C clocks. QSYNC then goes high again when the coincident rising edges of Bank A and Bank C occur. This feature is used primarily in applications where Bank A and Bank C are running at different frequencies, and is particularly useful when they are running at non-integer multiples of one another. Example Applications: 1. System Clock generator: Use a 16.66 MHz Crystal to generate eight 33.33MHz copies for PCI and four 100MHz copies for the CPU or PCI-X. 2. Line Card Multiplier: Multiply 19.44MHz from a back plane to 77.76MHz for the line Card ASICs and Serdes. 3. Zero Delay buffer for Synchronous memory: Fan out up to twelve 100MHz copies from a memory controller ref- erence clock to the memory chips on a memory module with zero delay. PIN ASSIGNMENT FSEL_B1 FSEL_B0 FSEL_A1 FSEL_A0 QA3 VDDO QA2 GNDO QA1 VDDO QA0 GNDO VCO_SEL 39 38 37 36 35 34 33 32 31 30 29 28 27 40 26 41 25 42 24 43 23 44 22 45 21 46 ICS87972I 20 47 19 48 18 49 17 50 16 51 15 52 14 1 2 3 4 5 6 7 8 9 10 11 12 13 FSEL_FB1 QSYNC GNDO QC0 VDDO QC1 FSEL_C0 FSEL_C1 QC2 VDDO QC3 GNDO INV_CLK 87972DYI 52-Lead LQFP 10mm x 10mm x 1.4mm package body Y package Top View www.icst.com/products/hiperclocks.html 1 REV. A OCTOBER 18, 2002 1 page Integrated Circuit Systems, Inc. TABLE 2. PIN CHARACTERISTICS Symbol C IN RPULLUP CPD ROUT Parameter Input Capacitance Input Pullup Resistor Power Dissipation Capacitance (per output) Output Impedance ICS87972I LOW SKEW, 1-TO-12 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER Test Conditions VDDA, VDD, VDDO = 3.465V Minimum Typical 51 Maximum 4 Units pF KΩ 25 pF 7Ω TABLE 3A. OUTPUT BANK CONFIGURATION SELECT FUNCTION TABLE Inputs FSEL_A1 FSEL_A0 00 01 10 11 Outputs QA ÷4 ÷6 ÷8 ÷12 Inputs FSEL_B1 FSEL_B0 00 01 10 11 Outputs QB ÷4 ÷6 ÷8 ÷10 Inputs FSEL_C1 FSEL_C0 00 01 10 11 Outputs QC ÷2 ÷4 ÷6 ÷8 TABLE 3B. FEEDBACK CONFIGURATION SELECT FUNCTION TABLE FSEL_FB2 0 0 0 0 1 1 1 1 Inputs FSEL_FB1 0 0 1 1 0 0 1 1 FSEL_FB0 0 1 0 1 0 1 0 1 Outputs QFB ÷4 ÷6 ÷8 ÷10 ÷8 ÷12 ÷16 ÷20 TABLE 3C. CONTROL INPUT SELECT FUNCTION TABLE Control Pin VCO_SEL REF_SEL CLK_SEL PLL_SEL nMR/OE INV_CLK Logic 0 VCO/2 CLK0 or CLK1 CLK0 BYPASS PLL Master Reset/Output Hi Z Non-Inverted QC2, QC3 Logic 1 VCO XTAL CLK1 Enable PLL Enable Outputs Inverted QC2, QC3 87972DYI www.icst.com/products/hiperclocks.html 5 REV. A OCTOBER 18, 2002 5 Page Integrated Circuit Systems, Inc. ICS87972I LOW SKEW, 1-TO-12 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER RELIABILITY INFORMATION TABLE 8. θJAVS. AIR FLOW TABLE qJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 58.0°C/W 42.3°C/W 200 47.1°C/W 36.4°C/W 500 42.0°C/W 34.0°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS87972I is: 8364 87972DYI www.icst.com/products/hiperclocks.html 11 REV. A OCTOBER 18, 2002 11 Page

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