|
|
PDF ICS87946-01 Data sheet ( Hoja de datos )
| Número de pieza | ICS87946-01 | |
| Descripción | LVPECL-TO-LVCMOS/LVTTL CLOCK GENERATOR | |
| Fabricantes | ICS | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de ICS87946-01 (archivo pdf) en la parte inferior de esta página. Total 13 Páginas | ||
|
No Preview Available !
www.DataSheet4U.com
Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS87946-01
LOW SKEW ÷1, ÷2
LVPECL-TO-LVCMOS/LVTTL CLOCK GENERATOR
GENERAL DESCRIPTION
The ICS87946-01 is a low skew, ÷1, ÷2 Clock
,&6 Generator and a member of the HiPerClockS™
HiPerClockS™ family of High Performance Clock Solutions from
ICS. The ICS87946-01 has one LVPECL clock
input pair. The PCLK, nPCLK pair can accept
LVPECL, CML, or SSTL input levels. The low impedance
LVCMOS outputs are designed to drive 50Ω series or parallel
terminated transmission lines. The effective fanout can be in-
creased from 10 to 20 by utilizing the ability of the outputs to
drive two series terminated lines.
The divide select inputs, DIV_SELx, control the output fre-
quency of each bank. The outputs can be utilized in the ÷1,
÷2 or a combination of ÷1 and ÷2 modes. The master reset
input, MR/nOE, resets the internal frequency dividers and also
controls the active and high impedance states of all outputs.
The ICS87946-01 is characterized at 3.3V core/3.3V output
and 3.3V core/2.5V output. Guaranteed bank, output and part-
to-part skew characteristics make the ICS87946-01 ideal for
those clock distribution applications demanding well defined
performance and repeatability.
FEATURES
• 10 single ended LVCMOS outputs, 7Ω typical output
impedance
• LVPECL clock input pair
• PCLK, nPCLK supports the following input levels:
LVPECL, CML, SSTL
• Maximum input frequency: 250MHz
• Output skew: 200ps (maximum)
• Part-to-part skew: 500ps (typical)
• Multiple frequency skew: 350ps (maximum)
• 3.3V input, outputs may be either 3.3V or 2.5V supply modes
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
BLOCK DIAGRAM
PIN ASSIGNMENT
PCLK
nPCLK
DIV_SELA
DIV_SELB
DIV_SELC
MR/nOE
÷1 0
÷2 1
0
1
0
1
QA0 - QA2
QB0 - QB2
QC0 - QC3
nc
VDD
PCLK
nPCLK
DIV_SELA
DIV_SELB
DIV_SELC
GND
32 31 30 29 28 27 26 25
1 24
2 23
3 22
4 ICS87946-01 21
5 20
6 19
7 18
8 17
9 10 11 12 13 14 15 16
GND
QB0
VDDB
QB1
GND
QB2
VDDB
VDDC
32-Lead LQFP
7mm x 7mm x 1.4mm
Y Package
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
87946AY-01
www.icst.com/products/hiperclocks.html
1
REV. A JANUARY 2, 2002
1 page  
Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS87946-01
LOW SKEW ÷1, ÷2
LVPECL-TO-LVCMOS/LVTTL CLOCK GENERATOR
TABLE
4D.
POWER
SUPPLY
DC
CHARACTERISTICS,
VDD
=
3.3V±5%,
V
DDX
=
2.5V±5%,
TA = 0°C TO 70°C
Symbol Parameter
Test Conditions Minimum Typical
VDD Positive Supply Voltage
*VDDx
Output Supply Voltage
IDD Core Supply Current
**IDDx
Output Supply Current
*V denotes V , V , V .
DDx DDA DDB DDC
**IDDx denotes IDDA, IDDB, IDDC.
3.135
2.375
3.3
2.5
41
8
Maximum
3.465
2.625
Units
V
V
mA
mA
TABLE 4E. LVCMOS DC CHARACTERISTICS, VDD = 3.3V±5%, VDDX = 2.5V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
V Input High Voltage
IH
2
VIL Input Low Voltage
-0.3
IIH
Input
High Current
DIV_SELA, DIV_SELB,
DIV_SELC, CLK_SEL,
nMR/OE
VDD = VIN = 3.465V
I
IL
Input
Low Current
DIV_SELA, DIV_SELB,
DIV_SELC, CLK_SEL,
nMR/OE
V = 3.465V, V = 0V
DD IN
-5
V + 0.3
DD
0.8
V
V
150 µA
µA
VOH Output High Voltage; NOTE 1
1.8
V Output Low Voltage; NOTE 1
OL
0.5
IOZL Output Tristate Current Low
TBD
IOZH Output Tristate Current High
TBD
NOTE 1: Outputs terminated with 50Ω to VDDx/2. See page 7, Figure 1B, 3.3V/2.5V Output Load Test Circuit.
V
V
V
V
TABLE 4F. LVPECL DC CHARACTERISTICS, VDD = VDDX = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
PCLK
IIH
Input High Current
nPCLK
VDD = VIN = 3.465V
VDD = VIN = 3.465V
PCLK
IIL
Input Low Current
nPCLK
VDD = 3.465V, VIN = 0V
VDD = 3.465V, VIN = 0V
-5
-150
VPP Peak-to-Peak Input Voltage
0.3
VCMR
Common Mode Input Voltage; NOTE 1, 2
GND + 1.5
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single ended applications, the maximum input voltage for PCLK and nPCLK is VDD + 0.3V.
150
5
1
VDD
Units
µA
µA
µA
µA
V
V
87946AY-01
www.icst.com/products/hiperclocks.html
5
REV. A JANUARY 2, 2002
5 Page 
Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS87946-01
LOW SKEW ÷1, ÷2
LVPECL-TO-LVCMOS/LVTTL CLOCK GENERATOR
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE
qJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
67.8°C/W
47.9°C/W
200
55.9°C/W
42.1°C/W
500
50.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS87946-01 is: 1204
87946AY-01
www.icst.com/products/hiperclocks.html
11
REV. A JANUARY 2, 2002
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet ICS87946-01.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| ICS87946-01 | LVPECL-TO-LVCMOS/LVTTL CLOCK GENERATOR | ICS |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |