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PDF EM78P5841 Data sheet ( Hoja de datos )
| Número de pieza | EM78P5841 | |
| Descripción | (EM78P5840 - EM78P5842) 8 BIT MICROCONTROLLER | |
| Fabricantes | ELAN Microelectronics | |
| Logotipo |  |
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EM78P5840/41/42
8-BIT MICRO-CONTROLLER
Version 2.6
ELAN MICROELECTRONICS CORP.
No. 12, Innovation 1st RD., Science-Based Industrial Park
Hsin Chu City, Taiwan, R.O.C.
TEL: (03) 5639977
FAX: (03) 5630118
1 page  
EM78P5840/5841/5842
8-bit Micro-controller
I. General Description
The EM78P5840 series are 8-bit RISC type microprocessor with low power, high speed CMOS technology. There
are 4Kx13 bits Electrical One Time Programmable Read Only Memory (OTP-ROM) within it. It provides security bits
and some One time programmable Option bits to protect the OTP memory code from any external access as well as to
meet user’s options.
This integrated single chip has an on_chip watchdog timer (WDT), program OTP-ROM, RAM, programmable real
time clock/counter, internal interrupt, power down mode, dual PWM (Pulse Width Modulation), 8-channel 10-bit A/D
converter and tri-state I/O.
II. Feature
CPU
· Operating voltage : 2.2V~5.5V at main CLK less then 3.58MHz.
Main CLK(Hz)
Under 3.58M
14.3M
Operating Voltage(min)
2.2V
3.6V
4k x 13 on chip Electrical One Time Programmable Read Only Memory (OTP-ROM)
144 x 8 on chip general propose RAM
Up to 19 bi-directional and 3 input only general purpose I/O
8 level stack for subroutine nesting
8-bit real time clock/counter (TCC)
One 8-bit counter interrupt
On-chip watchdog timer (WDT)
99.9 single instruction cycle commands
Three action modes in Crystal mode (Main clock can be programmed to 3.58M or 14.3M Hz)
Mode
CPU status Main clock 32.768kHz clock status
Sleep mode
Green mode
Turn off
Turn on
Turn off
Turn off
Turn off
Turn on
Normal mode Turn on
Turn on
Turn on
2 level Normal mode frequency: 3.58M and 14.3MHz.
Input port interrupt function
Dual clocks operation (Internal PLL main clock , External 32.768KHz)
Operating frequency mode
Crystal mode (XIN,XOUT pin connect external crystal and capacitance)
ERIC mode (ERCI pin connect resister to VDD)
IRC mode
PWM
Dual PWM (Pulse Width Modulation) with 10-bit resolution
Programmable period (or baud rate)
Programmable duty cycle
ADC
· Operating : 2.5V 5.5V
Converter Rate
74.6K
37.4K
18.7K
9.3K
Operating Voltage(min) 3.5V
3.0V
2.5V
2.5V
· 8 channel 10-bit successive approximation A/D converter
· Internal (VDD) reference voltage
POR
· Power-on reset
PACKAGE
EM78P5840M Æ 18 pin SOP, EM78P5841M Æ 20 pin SOP, EM78P5842M Æ 24 pin SOP
EM78P5840P Æ 18 pin PDIP, EM78P5841P Æ 20 pin PDIP, EM78P5842P Æ 24 pin PDIP
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to change without notice.
2004/11/10 V2.6
5 Page 
EM78P5840/5841/5842
8-bit Micro-controller
"ADD R2,A" allows a relative address be added to the current PC, and contents of the ninth and tenth bits are
cleared to "0''.
"TBL" allows a relative address added to the current PC, and contents of the ninth and tenth bits don't change.
The most significant bit (A10~A11) will be loaded with the contents of bit PS0~PS1 in the status register (R5
PAGE0) upon the execution of a "JMP'', "CALL'', "ADD R2, A'', or "MOV R2, A'' instruction.
If an interrupt is triggered, PROGRAM ROM will jump to address 0x08 at page0. The CPU will store ACC,
R3 status and R5 PAGE automatically, and they will be restored after instruction RETI.
R5(PAGE)
A11 A10
00
01
10
A9 A8 A7~A0
CALL
and
INTERRUPT
PAGE0 00000~003FF
PAGE1 00400~007FF
RET
RETL
RETI
PAGE2 00800~00BFF
STACK1
STACK2
STACK3
STACK4
STACK5
STACK6
STACK7
STACK8
store
ACC,R3,R5(PAGE)
restore
1 1 PAGE3 00C00~00FFF
Fig.3 Program counter organization
R3 (Status, Page selection)
(Status flag, Page selection bits)
7 6 5 43210
RPAGE1 RPAGE0 IOCPAGE T P Z DC C
R/W-0 R/W-0 R/W-0 R R R/W R/W R/W
Bit 0(C) : Carry flag
Bit 1(DC) : Auxiliary carry flag
Bit 2(Z) : Zero flag
Bit 3(P) : Power down bit
Set to 1 during power on or by a "WDTC" command and reset to 0 by a "SLEP" command.
Bit 4(T) : Time-out bit
Set to 1 by the "SLEP" and "WDTC" command, or during power up and reset to 0 by WDT timeout.
EVENT
T P REMARK
WDT wake up from sleep mode
0
0
WDT time out (not sleep mode)
0
1
/RESET wake up from sleep
10
Power up
11
Low pulse on /RESET
x X x : don't care
Bit 5(IOCPAGE) : change IOC5 ~ IOCE to another page
Please refer to Fig.4 control register configuration for details.
0/1 Î IOC page0 / IOC page1
Bit 6(RPAGE0 ~ RPAGE1) : change R5 ~ RE to another page
Please refer to VII.1 Operational registers for detail register configuration.
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to change without notice.
2004/11/10 V2.6
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet EM78P5841.PDF ] | |
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