PDF EM25LV512 Data sheet ( Hoja de datos )

Número de pieza	EM25LV512
Descripción	Flash Memory
Fabricantes	ELAN Microelectronics
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No Preview Available ! www.DataSheet4U.com EM25LV512 512 K (64K x 8) Bits Serial Flash Memory SPECIFICATION General Description The EM25LV512 is a 512K bits Flash memory organized as 64K x 8 bits and uses a single voltage of 2.7-3.6V for Program and Erase. It features a typical 2ms Page-Program time and a typical 40ms Block-Erase time. The device uses status register to detect the completion of the Program or Erase operation. To protect against inadvertent write, the device has on-chip hardware and software data protection schemes. The device offers typical 100,000 cycles endurance and a greater than 10 years data retention. The EM25LV512 conforms to SPI Bus compatible Serial Interface. It consisted of four pins (serial clock, chip select, serial data in, and serial data out) that support high-speed serial data transfers of up to 33MHz. The Hold pin, Write Protect pin, and Programmable Write Protect features provide flexible control. The EM25LV512 is offered in 8-lead SO package and known good die (KGD). For KGD, please contact ELAN Microelectronics or its representatives for detailed information (see Appendix at the bottom of this specification for Ordering Information). The EM25LV512 devices are suitable for applications that require memories with convenient and economical updating of program, data or configurations, e.g., Graphic cards, Hard disk drives, Networking cards, LCD monitors, Cordless Phones, etc. Features Single Power Supply • Full voltage range from 2.7 to 3.6 volts for both read and write operations • Regulated voltage range: 3.0 to 3.6 volts for both read and write operations Small block Erase Capability Block: Uniform 32K bytes Clock Rate • 33MHz (Maximum) Power Consumption • Active Current: 4mA (Typical) • Power-down Mode Standby current: 1µA (Typical) Page Program Features • Up to 256 Bytes in 2ms (Typical) Erase Features • Block-Erase Time: 40ms (Typical) • Chip-Erase Time: 40ms (Typical) Automatic Write Timing • Internal VPP Generation SPI Bus Compatible Serial Interface High Reliability: • Endurance cycles: 100K (Typical) • Data retention: 10 years Package Option • 8-lead-SO (150 mil) This specification is subject to change without further notice. (11.08.2004 V1.0) Page 1 of 30 1 page EM25LV512 512 K (64K x 8) Bits Serial Flash Memory SPECIFICATION Memory Organization The memory is organized as: 65,536 Bytes (8 bits per byte) 2 Blocks (256K bits or 32,768 bytes per block) 256 Pages (256 bytes per page) Each page can be individually programmed (bits are programmed from “1” to “0”). The device is Block or Chip Erasable (bits are erased from “0” to “1”), but not Page Erasable. Block 1 0 Address Range 8000h FFFFh 0000h 7FFFh Table 2: Memory Organization Hold# W# S# C D Q Control Logic I/O Buffer and Data Latches Address Register and Counter 256 Byte Data Buffer FFFFh Status Register Block1 8000h 7FFFh Block0 0000h 00FFh 256 Bytes (Page Size) Y-Decoder Size of the read-only memory area Figure 2: SPI Modes Supported This specification is subject to change without further notice. (11.08.2004 V1.0) Page 5 of 30 5 Page EM25LV512 512 K (64K x 8) Bits Serial Flash Memory SPECIFICATION Instructions All instructions, addresses, and data are shifted in and out of the device with the most significant bit shifted first. Serial Data Input (D) is sampled on the first rising edge of Serial Clock (C) after Chip Select (S#) is driven Low. Then, the one-byte instruction code must be shifted in to the device with the most significant bit entered first on Serial Data Input (D), and each bit being latched on the rising edges of Serial Clock (C). The instruction set is listed in Table 7 below. Depending on the instruction, the one-byte instruction code is followed by address bytes or data bytes, or both, or none at all. Chip Select (S#) must be driven High after the last bit of the instruction sequence has been shifted in. At the end of a Page Program (PP), Block Erase (BE), Chip Erase (CE), or Write Status Register (WRSR) instruction, Chip Select (S#) must be driven High exactly at a byte boundary. Otherwise the instruction will be rejected and not executed. That is, Chip Select (S#) must be driven High when the number of clock pulses after Chip Select (S#) being driven Low, is an exact multiple of eight. All attempts to access the memory array during a Write Status Register cycle, Program cycle, or Erase cycle are ignored, and the internal Write Status Register cycle, Program cycle, or Erase cycle will continue ineffectively. Instruction WREN WRDI RDSR WRSR READ FAST READ PP BE CE DP RES RDID Description One-byte Instruction Code Address Dummy Data Bytes Bytes Bytes Write Enable 0000 0110 0 00 Write Disable 0000 0100 0 00 Read Status Register 0000 0101 0 0 1 to ∞ Write Status Register 0000 0001 0 01 Read Data Bytes 0000 0011 3 0 1 to ∞ Read Data Bytes at Higher Speed 0000 1011 3 1 1 to ∞ Page Program 0000 0010 3 0 1 to 256 Block Erase 1101 1000 3 00 Chip Erase 1100 0111 0 00 Deep Power-down 1011 1001 0 00 Release from Deep Power-down, and Read Device ID 1010 1011 0 3 1 to ∞ Release from Deep Power-down 0 00 Read Manufacturer/Device ID 1001 0000 0 3 1 to ∞ Table 7: Instruction Set This specification is subject to change without further notice. (11.08.2004 V1.0) Page 11 of 30 11 Page

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