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PDF PE4230 Data sheet ( Hoja de datos )

Número de pieza PE4230
Descripción SPDT High Power UltraCMOS RF Switch
Fabricantes Peregrine Semiconductor 
Logotipo Peregrine Semiconductor Logotipo



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Product Description
The PE4230 UltraCMOS™ RF Switch is designed to cover a
broad range of applications from DC through 3000 MHz. This
single-supply reflective switch integrates on-board CMOS
control logic driven by a simple, single-pin CMOS or TTL
compatible control input. Using a nominal +3-volt power supply,
a typical input 1 dB compression point of +32 dBm can be
achieved. The PE4230 also exhibits input-output isolation of
better than 39 dB at 1000 MHz and is offered in a small 8-lead
MSOP package.
The PE4230 SPDT High Power UltraCMOS™ RF Switch is
manufactured in Peregrine’s patented Ultra Thin Silicon
(UTSi®) CMOS process, offering the performance of GaAs with
the economy and integration of conventional CMOS.
Figure 1. Functional Diagram
RFC
Product Specification
PE4230
SPDT High Power UltraCMOS™
RF Switch
Features
Single 3-volt power supply
Low insertion loss: 0.35 dB at
1000 MHz, 0.55 dB at 2000 MHz
High isolation of 39 dB at 1000 MHz,
30 dB at 2000 MHz
Typical input 1 dB compression point
of +32 dBm
Single-pin CMOS or TTL logic control
Low cost
Figure 2. Package Type
8-lead MSOP
RF1 RF2
CMOS
Control
Driver
CTRL
Table 1. Electrical Specifications @ +25 °C, VDD = 3 V (ZS = ZL = 50 )
Parameter
Conditions
Minimum
Typical
Maximum
Units
Operation Frequency1
DC
3000
MHz
Insertion Loss
Isolation – RFC to RF1/RF2
Isolation – RF1 to RF2
Return Loss
1000 MHz
2000 MHz
1000 MHz
2000 MHz
1000 MHz
2000 MHz
1000 MHz
2000 MHz
0.35 0.45
0.55 0.65
38 39
28 30
33.5 35
26.5
23.5
28
25.5
14.5 15.4
dB
dB
dB
dB
dB
dB
dB
dB
‘ON’ Switching Time
CTRL to 0.1 dB final value, 2 GHz
200
ns
‘OFF’ Switching Time
CTRL to 25 dB isolation, 2 GHz
90 ns
Video Feedthrough2
Input 1 dB Compression
2000 MHz
15
30 32
mVpp
dBm
Input IP3
2000 MHz, 17 dBm
50
Notes: 1. Device linearity will begin to degrade below 10 MHz.
2. The DC transient at the output of any port of the switch when the control voltage is switched from Low to
High or High to Low in a 50 test set-up, measured with 1ns risetime pulses and 500 MHz bandwidth.
dBm
Document No. 70-0029-02 www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
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PE4230 pdf
PE4230
Product Specification
Evaluation Kit
The SPDT Switch Evaluation Kit board was
designed to ease customer evaluation of the
PE4230 SPDT switch. The RF common port is
connected through a 50 transmission line to the
top left SMA connector, J1. Port 1 and Port 2 are
connected through 50 transmission lines to the
top two SMA connectors on the right side of the
board, J3 and J4. A through transmission line
connects SMA connectors J6 and J8. This
transmission line can be used to estimate the loss
of the PCB over the environmental conditions
being evaluated.
The board is constructed of a two metal layer FR4
material with a total thickness of 0.031”. The
bottom layer provides ground for the RF
transmission lines. The transmission lines were
designed using a coplanar waveguide with ground
plane model using a trace width of 0.030”, trace
gaps of 0.007”, dielectric thickness of 0.028”,
metal thickness of 0.0014” and εr of 4.4.
J2 provides a means for controlling DC and digital
inputs to the device. Starting from the lower left
pin, the second pin to the right (J2-3) is connected
to the device CNTL input. The fourth pin to the
right (J2-7) is connected to the device VDD input.
A decoupling capacitor (100 pF) is provided on
both CNTL and VDD traces. It is the responsibility
of the customer to determine proper supply
decoupling for their design application. Removing
these components from the evaluation board has
not been shown to degrade RF performance.
Figure 12. Evaluation Board Layouts
Peregrine Specification 101/0037
Figure 13. Evaluation Board Schematic
Peregrine Specification 102/0035
Document No. 70-0029-02 www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
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