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PDF IDT728981 Data sheet ( Hoja de datos )

Número de pieza IDT728981
Descripción TIME SLOT INTERCHANGE DIGITAL SWITCH 128 x 128
Fabricantes IDT 
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TIME SLOT INTERCHANGE
DIGITAL SWITCH
128 x 128
IDT728981
.EATURES:
128 x 128 channel non-blocking switch
Serial Telecom Bus Compatible (ST-BUS®)
4 RX inputs—32 channels at 64 Kbit/s per serial line
4 TX output—32 channels at 64 Kbit/s per serial line
Three-state serial outputs
Microprocessor Interface (8-bit data bus)
5V Power Supply
Available in 44-pin Plastic Leaded Chip Carrier (PLCC), 40-pin
Plastic Dip (P-DIP) and 44-pin Plastic Quad Flatpack (PQFP)
Operating Temperature Range -40°C to +85°C
DESCRIPTION:
The IDT728981 is a ST-BUS® compatible digital switch controlled by a
microprocessor. The IDT728981 can handle as many as 128, 64 Kbit/s input
and output channels. Those 128 channels are divided into 4 serial inputs and
outputs, each of which consists of 32 channels (64 Kbit/s per channel) to form
a multiplexed 2.048 Mb/s stream.
.UNCTIONAL DESCRIPTION
A functional block diagram of the IDT728981 device is shown below. The
serial streamsoperatecontinuouslyat2.048Mb/sandarearrangedin125µs
wide frames each containing 32, 8-bit channels. Four input (RX0-3) and four
output (TX0-3) serial streams are provided in the IDT728981 device allowing
a complete 128 x 128 channel non-blocking switch matrix to be constructed.
The serial interface (C4i) clock for the device is 4.096 MHz.
The received serial data is internally converted to a parallel format by the on
chip serial-to-parallel converters and stored sequentially in a 128-position Data
Memory. By using an internal counter that is reset by the input 8 KHz frame pulse,
F0i, the incoming serial data streams can be framed and sequentially ad-
dressed.
.UNCTIONAL BLOCK DIAGRAM
C4i F0i VCC GND
ODE
RX0
Receive
RX1 Serial Data
RX2 Streams
RX3
Timing
Unit
Output MUX
Data
Memory
Control Register
Microprocessor Interface
Connection
Memory
DS CS R/W A0/ DTA D0/
A5 D7
Transmit
Serial Data
Streams
TX0
TX1
TX2
TX3
5703 drw01
2001 Integrated Device Technology, Inc.
1
JANUARY 2001
DSC-5703/1

1 page




IDT728981 pdf
IDT728981 Time Slot Interchange
Digital Switch 128 x 128
Commercial Temperature Range
Mode Control
Memory Select
Stream Address
Bits
(unused)
Bits (unused)
Bits
76543210
Bit Name
Description
7 SM (Split Memory)
When 1, all subsequent reads are from the Data Memory and writes are to the Connection Memory LOW, except
when the Control Register is accessed again. When 0, the Memory Select bits specify the memory for the
operations. In either case, the Stream Address Bits select the subsection of the memory which is made available.
6 PE (Processor Mode) When 1, the contents of the Connection Memory LOW are output on the Serial Output streams except when the ODE
pin is LOW. When 0, the Connection Memory bits for each channel determine what is output.
5 unused
4-3 MS1-MS0
(Memory Select Bits)
0-0 - Not to be used.
0-1 - Data Memory (read only from the microprocessor port)
1-0 - Connection Memory LOW
1-1 - Connection Memory is HIGH
2 unused
1-0 STA1-0
The number expressed in binary notation on these bits refers to the input or output stream which corresponds to the
(Stream Address Bits) subsection of memory made accessible for subsequent operations.
Table 3. Control Register Configuration
No Corresponding Memory
- These bits give 0s if read
7654
CS (unused) OE
3210
Bit Name
2 CS (Channel Source)
1
0 OE (Output Enable)
Description
When 1, the contents of the corresponding location in Connection Memory LOW are output on the location's channel
and stream. When 0, the contents of the corresponding location in Connection Memory LOW act as an address for the
Data Memory and determine the source of the connection to the location's channel and stream.
unused
If the ODE pin is HIGH and bit 6 of the Control Register is 0, then this bit enables the output driver for the location's
channel and stream. This allows individuals channels on individuals streams to be made high-impedance, allowing
switching matrices to be constructed. A 1 enables the driver and a 0 disables it.
Table 4. Connection Memory High Register
Stream Address
(unused)
Bits
Channel Address Bits
7654321
0
Bit Name
Description
7 unused
6-5(1) Stream Address Bits
The number expressed in binary notation on these 2 bits are the number of the stream for the source of the connection.
Bit 6 is the most significant bit, e.g., If bit 6 is 1, bit 5 is 0 then the source of the connection is a channel on RX2.
4-0(1) Channel Address Bits
The number expressed in binary notation on these 5 bits is the number of the channel which is the source of the
connection (the stream where the channel lies is defined by bits 7, 6 and 5). Bit 4 is the most significant bit, e.g., if bit 4
is 1, bit 3 is 0, bit 2 is 0, bit 1 is 1 and bit 0 is 1, then the source of the connection is channel 19.
NOTE:
1. If bit 2 of the corresponding Connection HIGH location is 1 or bit 6 of the Control Register is 1, then these entire 8 bits are output on the channel and stream associated with
this location. Otherwise, the bits are used as indicated to define the source of the connection which is output on the channel and stream associated with this location.
Table 5. Connection Memory Low Register
5

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