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PDF S29NS-N Data sheet ( Hoja de datos )

Número de pieza S29NS-N
Descripción Burst Mode Flash Memory
Fabricantes SPANSION 
Logotipo SPANSION Logotipo



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S29NS-N MirrorBit™ Flash Family
S29NS256N, S29NS128N, S29NS064N
256/128/64 Megabit (16/8/4M x 16-bit), CMOS 1.8 Volt-only
Simultaneous Read/Write, Multiplexed, Burst Mode
Flash Memory
S29NS-N MirrorBit™ Flash Family Cover Sheet
Data Sheet (Advance Information)
Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. Each product described herein may be designated as Advance Information,
Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions.
Publication Number S29NS-N_00 Revision A Amendment 12 Issue Date June 13, 2006

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S29NS-N pdf
Data Sheet (Advance Information)
The host system can detect whether a program or erase operation is complete by using the device status bit
DQ7 (Data# Polling) and DQ6/DQ2 (toggle bits). After a program or erase cycle has been completed, the
device automatically returns to reading array data.
The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the
data contents of other sectors. The devices are fully erased when shipped from the factory.
Hardware data protection measures include a low VCC detector that automatically inhibits write operations
during power transitions. The devices also offer three types of data protection at the sector level. Persistent
Sector Protection provides in-system, command-enabled protection of any combination of sectors using a
single power supply at VCC. Password Sector Protection prevents unauthorized write and erase operations
in any combination of sectors through a user-defined 64-bit password. When at VIL, WP# locks the highest
two sectors. Finally, when ACC is at VIL, all sectors are locked.
The devices offer two power-saving features. When addresses have been stable for a specified amount of
time, the device enters the automatic sleep mode. The system can also place the device into the standby
mode. Power consumption is greatly reduced in both modes.
Device programming occurs by executing the program command sequence. This initiates the Embedded
Program algorithm - an internal algorithm that automatically times the program pulse widths and verifies
proper cell margin. The Unlock Bypass mode facilitates faster program times by requiring only two write
cycles to program data instead of four. Additionally, Write Buffer Programming is available on this family of
devices. This feature provides superior programming performance by grouping locations being programmed.
Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase
algorithm - an internal algorithm that automatically preprograms the array (if it is not already fully
programmed) before executing the erase operation. During erase, the device automatically times the erase
pulse widths and verifies proper cell margin.
The Program Suspend/Program Resume feature enables the user to put program on hold to read data from
any sector that is not selected for programming. If a read is needed from the Persistent Protection area,
Dynamic Protection area, or the CFI area, after an program suspend, then the user must use the proper
command sequence to enter and exit this region. The program suspend/resume functionality is also available
when programming in erase suspend (1 level depth only).
The Erase Suspend/Erase Resume feature enables the user to put erase on hold to read data from, or
program data to, any sector that is not selected for erasure. True background erase can thus be achieved. If
a read is needed from the Persistent Protection area, Dynamic Protection area, or the CFI area, after an
erase suspend, then the user must use the proper command sequence to enter and exit this region.
The hardware RESET# pin terminates any operation in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor to read boot-up firmware from the Flash memory
device.
The host system can detect whether a memory array program or erase operation is complete by using the
device status bit DQ7 (Data# Polling), DQ6/DQ2 (toggle bits), DQ5 (exceeded timing limit), DQ3 (sector erase
start timeout state indicator), and DQ1 (write to buffer abort). After a program or erase cycle has been
completed, the device automatically returns to reading array data.
The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully erased when shipped from the factory.
Hardware data protection measures include a low VCC detector that automatically inhibits write operations
during power transitions. The device also offers two types of data protection at the sector level. When at VIL,
WP# locks the two outermost boot sectors at the top of memory.
When the ACC pin = VIL, the entire flash memory array is protected.
Spansion LLC Flash technology combines years of Flash memory manufacturing experience to produce the
highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a
sector. The data is programmed using hot electron injection.
S29NS-N_00_A12 June 13, 2006
S29NS-N MirrorBit™ Flash Family
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S29NS-N arduino
Data Sheet (Advance Information)
5. Connection Diagram
5.1 S29NS256N – 48-Ball Very Thin FBGA Connection Diagram
S29NS256N
48-Ball Very Thin FBGA
Top View, Balls Facing Down
NC
NC
NC
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10
RDY A21 VSS CLK VCC WE# ACC A19 A17 A22
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10
VCCQ A16 A20 AVD# A23 RESET# WP# A18 CE# VSSQ
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10
VSS A/DQ7 A/DQ6A/DQ13A/DQ12A/DQ3 A/DQ2 A/DQ9 A/DQ8 OE#
D1 D2 D3 D4 D5 D6 D7 D8 D9 D10
A/DQ15A/DQ14 VSSQ A/DQ5 A/DQ4A/DQ11A/DQ10 VCCQ A/DQ1 A/DQ0
NC
NC
NC
NC
NC
S29NS-N_00_A12 June 13, 2006
S29NS-N MirrorBit™ Flash Family
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