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PDF S29NS128J Data sheet ( Hoja de datos )

Número de pieza S29NS128J
Descripción Burst Mode Flash Memories
Fabricantes SPANSION 
Logotipo SPANSION Logotipo



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S29NS-J
128 Megabit (8 M x 16-Bit), 64 Megabit (4 M x 16-Bit),
32 Megabit (2 M x 16-Bit), and 16 Megabit (1 M x 16 Bit),
110 nm CMOS 1.8-Volt only Simultaneous Read/Write,
Burst Mode Flash Memories
Data Sheet
Notice to Readers: This document states the current technical specifications
regarding the Spansion product(s) described herein. Spansion LLC deems the
products to have been in sufficient production volume such that subsequent
versions of this document are not expected to change. However, typographical
or specification corrections, or modifications to the valid combinations offered
may occur.
Publication Number S29NS-J_01 Revision A Amendment 10 Issue Date March 22, 2006

1 page




S29NS128J pdf
S29NS-J
128 Megabit (8 M x 16-Bit), 64 Megabit (4 M x 16-Bit),
32 Megabit (2 M x 16-Bit), and 16 Megabit (1 M x 16 Bit),
110 nm CMOS 1.8 Volt-only Simultaneous Read/Write,
Burst Mode Flash Memories
Data Sheet
Distinctive Characteristics
„ Single 1.8 volt read, program and erase
(1.7 to 1.95 V)
„ Multiplexed Data and Address for reduced
I/O count
— A15–A0 multiplexed as DQ15–DQ0
— Addresses are latched by AVD# control input when
CE# low
„ Simultaneous Read/Write operation
— Data can be continuously read from one bank while
executing erase/program functions in other bank
— Zero latency between read and write operations
„ Read access times at 66/54 MHz (CL=30 pF)
— Burst access times of 11/13.5 ns
at industrial temperature range
— Asynchronous random access times
of 65/70 ns
— Synchronous random access times
of 71/87.5 ns
„ Burst Modes
— Continuous linear burst
— 8/16/32 word linear burst with wrap around
— 8/16/32 word linear burst without wrap around
„ Power dissipation (typical values, 8 bits
switching, CL = 30 pF)
— Burst Mode Read: 25 mA
— Simultaneous Operation: 40 mA
— Program/Erase: 15 mA
— Standby mode: 9 µA
„ Sector Architecture
— Four 8 Kword sectors
— Two hundred fifty-five (S29NS128J), one hundred
twenty-seven (S29NS064J),sixty-three
(S29NS032J), or thirty-one (S29NS016J) 32 Kword
sectors
— Four banks (see next page for sector count and size)
„ Sector Protection
— Software command sector locking
— WP# protects the two highest sectors
— All sectors locked when Acc = VIL
„ Handshaking feature
— Provides host system with minimum possible latency
by monitoring RDY
„ Supports Common Flash Memory Interface
(CFI)
„ Software command set compatible with
JEDEC 42.4 standards
— Backwards compatible with Am29F and Am29LV
families
„ Manufactured on 110 nm process technology
„ Embedded Algorithms
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically writes
and verifies data at specified addresses
„ Data# Polling and toggle bits
— Provides a software method of detecting program and
erase operation completion
„ Erase Suspend/Resume
— Suspends an erase operation to read data from, or
program data to, a sector that is not being erased,
then resumes the erase operation
„ Hardware reset input (RESET#)
— Hardware method to reset the device for reading
array data
„ CMOS compatible inputs and outputs
„ Package
— 48-ball Very Thin FBGA (S29NS128J)
— 44-ball Very Thin FBGA (S29NS064J, S29NS032J,
S29NS016J)
„ Cycling Endurance: 1 million cycles per sector
typical
„ Data Retention: 20 years typical
Publication Number S29NS-J_00 Revision A Amendment 10 Issue Date March 22, 2006

5 Page





S29NS128J arduino
Data Sheet
Connection Diagram
S29NS064J
44-Ball Very Thin FBGA (VDD044)
Top View, Balls Facing Down
NC
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10
RDY A21 GND CLK VCC WE# VPP A19 A17 NC
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10
VCC A16 A20 AVD# NC RESET# WP# A18 CE# GND
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10
GND A/DQ7 A/DQ6 A/DQ13 A/DQ12 A/DQ3 A/DQ2 A/DQ9 A/DQ8 OE#
D1 D2 D3 D4 D5 D6 D7 D8 D9 D10
A/DQ15 A/DQ14 GND A/DQ5 A/DQ4 A/DQ11A/DQ10 VCC A/DQ1 A/DQ0
NC
NC NC
March 22, 2006 S29NS-J_00_A10
S29NS-J
7

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