PDF IDT74SSTVF16859 Data sheet ( Hoja de datos )

Número de pieza	IDT74SSTVF16859
Descripción	13-BIT TO 26-BIT REGISTERED BUFFER
Fabricantes	IDT
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No Preview Available ! www.DataSheet4U.com IDT74SSTVF16859 13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O COMMERCIAL TEMPERATURE RANGE 13-BIT TO 26-BIT REGISTERED IDT74SSTVF16859 BUFFER WITH SSTL I/O FEATURES: • 1:2 register buffer • Meets or exceeds JEDEC standard SSTVF16859 • 2.3V to 2.7V Operation for PC1600, PC2100, and PC2700 • 2.5V to 2.7V Operation for PC3200 • SSTL_2 Class I style data inputs/outputs • Differential CLK input • RESET control compatible with LVCMOS levels • Latch-up performance exceeds 100mA • ESD >2000V per MIL-STD-883, Method 3015; >200V using machine model (C = 200pF, R = 0) • Available in 56 pin VFQFPN and 64 pin TSSOP packages APPLICATIONS: • Along with CSPT857C, Zero Delay PLL Clock buffer, provides complete solution for DDR1 DIMMs DESCRIPTION: The SSTVF16859 is a 13-bit to 26-bit registered buffer designed for 2.3V-2.7V VDD for PC1600 - PC2700 and 2.5V-2.7V VDD for PC3200, and supports low standby operation. All data inputs and outputs are SSTL_2 level compatible with JEDEC standard for SSTL_2. RESET is an LVCMOS input since it must operate predictably during the power-up phase. RESET, which can be operated independent of CLK and CLK, must be held in the low state during power-up in order to ensure predictable outputs (low state) before a stable clock has been applied. RESET, when in the low state, will disable all input receivers, reset all registers, and force all outputs to a low state, before a stable clock has been applied. With inputs held low and a stable clock applied, outputs will remain low during the Low-to-High transition of RESET. FUNCTIONAL BLOCK DIAGRAM RESET 51 CLK CLK VREF D1 48 49 45 35 1D C1 R 16 Q1A 32 Q1B TO 12 OTHER CHANNELS The IDT logo is a registered trademark of Integrated Device Technology, Inc. COMMERCIAL TEMPERATURE RANGE c 2003 Integrated Device Technology, Inc. 1 AUGUST 2003 DSC-6194/13 1 page IDT74SSTVF16859 13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O COMMERCIAL TEMPERATURE RANGE TIMING REQUIREMENTS OVER RECOMMENDED OPERATING FREE-AIR TEMPERATURE RANGE PC1600 - PC2700 PC3200 Symbol Parameter Min. Max. Min. Max. CLOCK Clock Frequency — 200 — 220 tw Pulse Duration, CLK, CLK HIGH or LOW 2.5 — 2.5 — tACT Differential Inputs Active Time(1) — 22 — 22 tINACT DifferentialInputsInactiveTime(2) — 22 — 22 tSU Setup Time, Fast Slew Rate(3,5) Data Before CLK↑, CLK↓ 0.65 — 0.65 — Setup Time, Slow Slew Rate(4, 5) 0.75 — 0.75 — tH Hold Time, Fast Slew Rate(3,5) Data Before CLK↑, CLK ↓ 0.75 — 0.65 — Hold Time, Slow Slew Rate(2,5) 0.9 — 0.8 — NOTES: 1. Data inputs must be low a minimum time of tACT max., after RESET is taken HIGH. 2. Data and clock inputs must be held at valid levels (not floating) a minimum time of tINACT max., after RESET is taken LOW. 3. For data signal input slew rate is ≥1V/ns. 4. For data signal input slew rate is ≥0.5V/ns and <1V/ns. 5. CLK, CLK signal input slew rates are ≥1V/ns. Unit MHz ns ns ns ns ns ns ns SWITCHING CHARACTERISTICS OVER RECOMMENDED FREE-AIR OPERATING RANGE (UNLESS OTHERWISE NOTED) Symbol fMAX tPDM tPDMSS tPHL Parameter CLK and CLK to Q CLK and CLK to Q (simultaneous switching) RESET to Q PC1600 - PC2700 Min. Max. 200 — 1.1 2.6 — 2.9 —5 PC3200 Min. 220 1.1 — — Max. — 2.4 2.68 5 Unit MHz ns ns ns 5 5 Page

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IDT74SSTVF16859	13-BIT TO 26-BIT REGISTERED BUFFER	IDT

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