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PDF T6K01 Data sheet ( Hoja de datos )
| Número de pieza | T6K01 | |
| Descripción | COLUMN DRIVER LSI | |
| Fabricantes | Toshiba Semiconductor | |
| Logotipo |  |
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T6K01
TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
T6K01
COLUMN DRIVER LSI FOR A DOT MATRIX GRAPHIC LCD
The T6K01 is a column (segment) driver for a dot matrix graphic
LCD. The T6K01 offers low power consumption, due to the CMOS
Si-Gate process. It is designed to interface directly with a
microprocessor unit (MPU). A program running on the MPU can
drive the T6K01 asynchronously. The T6K01 stores data
transferred from the MPU in its built-in RAM.
The data stored in the built-in display RAM corresponds to the
image on the LCD screen; the data is converted into the LCD
drive signal. A configuration of two T6K01s and one T6C03 can be
used to drive a 480 × 160-dot LCD.
Features
l Dot matrix graphic LCD column driver with display RAM
l Display RAM capacity: 160 lines × 240 outputs = 38400 bits
l LCD drive output: 240
l Interface: 8-bit MPU
l Relation between RAM data and display
RAM bit data = 1 → display ON
RAM bit data = 0 → display OFF
l Display OFF function
l Low power consumption
l Logic power supply: 2.7 to 3.3 V
l LCD power supply: 8.0 to 26.0 V
l CMOS Process
l Package: TCP (Tape Carrier Package)
1 2002-01-07
1 page  
T6K01
Function of Each Block
● RAM cell
The RAM capacity is 160 lines × 240 outputs for a total of 38400 bits.
● DIR
This circuit changes the data flow direction and page selection sequence.
● Address decoder
This decoder selects one RAM address for read / write operation.
● 8-bit counter + decoder
The decoder selects one RAM cell from the 160 address lines for display operation.
● Latch
The data is latched from the display RAM on the falling edge of CL.
● Column driver circuit and LCD voltage generation circuit
The T6K01 has 240 column drivers and four different LCD drive output voltage levels. The display data
from the latch circuit and the M signal determine which of the four LCD drive voltages is selected. This
circuit is shown in the following diagram.
Relation Between FR, Data Input and Output Level
/ DSPOF
L
H
H
H
H
*: INVALID
FR Input Data (RAM Data)
**
LL
LH
HL
HH
Output Level
VSS / VLC5
VLC3
VSS / VLC5
VLC2
VLC0
5 2002-01-07
5 Page 
AC Characteristics (2)
display data
T6K01
Test Conditions (Unless Otherwise Noted, VSS = 0 V, VDD = 3.0 V ± 10%, Ta = −20 to 75°C)
Item
CL Pulse Width H
CL Pulse Width L
CL Rise / Fall Time
FP Set-up Time
FP Hold Time
Symbol
tCWH
tCWL
tr, tf
tFSU
tFHD
Pin Name
CL
CL
CL
FP
FP
Min Max Unit
500 ―
ns
500 ―
ns
― 50 ns
100 ―
ns
100 ―
ns
AC Characteristics (3)
Item
CL-to-FP-margin time
FP-to-CL-margin time
Symbol
tCF
tFC
Condition
Min Max Unit
20 ― ns
0 ― ns
11 2002-01-07
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet T6K01.PDF ] | |
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