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PDF M36L0R7060L1 Data sheet ( Hoja de datos )
| Número de pieza | M36L0R7060L1 | |
| Descripción | (M36L0R70x0x1) Flash memory | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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M36L0R7060U1 M36L0R7060L1
M36L0R7050U1 M36L0R7050L1
128 Mbit (Mux I/O, Multiple Bank, Multi-Level, Burst) Flash
memory, 32 or 64 Mbit PSRAM, 1.8V supply Multi-Chip Package
Preliminary Data
Feature summary
■ Multi-Chip Package
– 1 die of 128 Mbit (8Mb x16, Mux I/O
Multiple Bank, Multi-level, Burst) Flash
Memory
– 1 die of 32 or 64Mbit Mux I/O, Burst
Pseudo SRAM
■ Supply voltage
– VDDF = VDDP = VDDQF = 1.7 to 1.95V
– VPPF = 9V for fast program
■ Electronic signature
– Manufacturer Code: 20h
– Device Codes (Top Flash Configuration):
M36L0R7060U1: 882Eh,
M36L0R7050U1: 882Eh
– Device Codes (Bottom Flash Configuration)
M36L0R7060L1: 882Fh
M36L0R7050L1: 882Fh
■ ECOPACK® package
Flash memory
■ Multiplexed address/data
■ Synchronous / asynchronous read
– Synchronous Burst Read mode: 66MHz
– Random Access: 85ns
■ Synchronous burst read suspend
programming time
– 10µs typical Word program time using
Buffer Enhanced Factory Program
command
■ Memory organization
– Multiple Bank Memory Array: 8 Mbit Banks
– Parameter Blocks (Top or Bottom location)
■ Security
– 64 bit unique device number
– 2112 bit user programmable OTP Cells
■ 100,000 program/erase cycles per block
FBGA
TFBGA88 (ZAM)
8 x 10mm
■ Dual operations
– program/erase in one Bank while read in
others
– No delay between Read and Write
operations
■ Block locking
– All blocks locked at power-up
– Any combination of blocks can be locked
with zero latency
– WPF for Block Lock-Down
– Absolute Write Protection with VPPF = VSS
■ Common Flash Interface (CFI)
PSRAM
■ Access time: 70ns
■ Synchronous modes:
– Synchronous Write: continuous burst
– Synchronous Read: continuous burst or
fixed length: 4, 8 or 16 Words for 32 Mbit
devices or 4, 8,16 or 32 Words for 64 Mbit
devices
– Maximum Clock Frequency: 83MHz
■ Low power consumption
■ Low power features
– Partial Array Self-Refresh (PASR)
– Deep Power-Down (DPD) Mode
– Automatic Temperature-compensated Self-
Refresh
June 2006
Rev 1
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
1/22
www.st.com
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1 page  
M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
TFBGA connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
TFBGA88 8 × 10mm, 8 × 10 ball array - 0.8mm pitch, bottom view package outline. . . . . 19
5/22
5 Page 
M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1
Signal descriptions
2.6 Flash memory Chip Enable (EF)
The Chip Enable input activates the memory control logic, input buffers, decoders and
sense amplifiers. When Chip Enable is at VILand Reset is at VIH the device is in active
mode. When Chip Enable is at VIH the memory is deselected, the outputs are high
impedance and the power consumption is reduced to the stand-by level.
It is not allowed to set both EF and EP to VIL at the same time.
2.7 Flash memory Output Enable (GF)
The Output Enable input controls data outputs during the Bus Read operation of the Flash
memory.
2.8 Flash memory Write Enable (WF)
The Write Enable input controls the Bus Write operation of the Flash memory’s Command
Interface. The data and address inputs are latched on the rising edge of Chip Enable or
Write Enable whichever occurs first.
2.9 Flash memory Write Protect (WPF)
Write Protect is an input that gives an additional hardware protection for each block. When
Write Protect is at VIL, the Lock-Down is enabled and the protection status of the Locked-
Down blocks cannot be changed. When Write Protect is at VIH, the Lock-Down is disabled
and the Locked-Down blocks can be locked or unlocked. (refer to M58LRxxxGUL
datasheet).
2.10
2.11
Flash memory Reset (RPF)
The Reset input provides a hardware reset of the memory. When Reset is at VIL, the
memory is in reset mode: the outputs are high impedance and the current consumption is
reduced to the Reset Supply Current IDD2. Refer to the M58LRxxxGUL datasheet for the
value of IDD2. After Reset all blocks are in the Locked state and the Configuration Register is
reset. When Reset is at VIH, the device is in normal operation. Exiting reset mode the device
enters asynchronous read mode, but a negative transition of Chip Enable or Latch Enable is
required to ensure valid data outputs.
The Reset pin can be interfaced with 3V logic without any additional circuitry. It can be tied
to VRPH (refer to the M58LRxxxGUL datasheet).
PSRAM Chip Enable (EP)
Chip Enable, EP, activates the device when driven Low (asserted). When de-asserted (VIH),
the device is disabled and goes automatically in low-power Standby mode or Deep Power-
Down mode, according to the RCR settings.
It is not allowed to set both EF and EP to VIL at the same time.
11/22
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