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PDF TC25C25 Data sheet ( Hoja de datos )
| Número de pieza | TC25C25 | |
| Descripción | BICMOS PWM CONTROLLERS | |
| Fabricantes | TelCom Semiconductor | |
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1
TC25C25
TC35C25
BICMOS PWM CONTROLLERS
FEATURES
s Low Power BICMOS Construction
s Low Supply Current at 20 kHz ............... 1.0mA Typ
s Latch-Up Immunity ................. >500mA on Outputs
s Below Rail Input Protection .............................. – 5V
s High Output Drive ................................ 500mA Peak
s Fast Rise/Fall Time ..................... 50nsec @ 1000pF
s High Frequency Operation .................. Up to 1MHz
s Tri-state Sync Pin for Easy Parallel Operation
s Under Voltage Hysteresis Guaranteed
s Shutdown Pin Available
s Double-Ended
s Soft Start, With Small Cap
s Low Prop Delay Shutdown to
Output ................................................. 140nsec Typ.
ORDERING INFORMATION
Part No.
TC25C25EOE
TC25C25EPE
TC35C25COE
TC35C25CPE
Configuration Pkg./Temperature
Non-Inverting 16-Pin SOIC (Wide)
– 40°C to +85°C
Non-Inverting 16-Pin Plastic DIP (Narrow)
– 40°C to +85°C
Non-Inverting 16-Pin SOIC (Wide)
0°C to +70°C
Non-Inverting 16-Pin Plastic DIP (Narrow)
0°C to +70°C
GENERAL DESCRIPTION
The TC35C25 family of PWM controllers are CMOS
implementations of the industry standard 3525 voltage
mode SMPS ICs.
These second generation CMOS devices employ
TelCom Semiconductors' Tough BiCMOS™ process for
latch-up proof operation. They offer much lower power
consumption than any of their previous CMOS or bipolar
counterparts.
These controllers have separate supply pins for the
control and output sections of the circuit. This allows "boot-
strap" operation. The CMOS output stage allows the output
voltage to swing to within 25mV of either rail.
Other improved features include tighter hysteresis and
undervoltage start-up specifications over temperature, and
very low input bias current on all inputs.
2
3
4
5
FUNCTIONAL BLOCK DIAGRAM
VREF
VI+N
GND
SYNC
RT
CT
DISCH
16
15
12
3
6
5
7
UNDER
VOLTAGE
REFERENCE
REGULATOR
+4V REF
OSC OUT
4
+6V
OSC
FLIP
FLOP
COMP 9
IN– 1
IN+ 2
ERROR
AMP
SOFT
START
SHUTDOWN
8
10
CMPTR
+6V
50µA
R
S
PWM
LATCH
R
TELCOM SEMICONDUCTOR, INC.
35C25
13
VDD
11
A
14
B
6
7
8
TC25/35C25-2 10/1/96
4-111
1 page  
BICMOS PWM CONTROLLERS
1
TC25C25
TC35C25
OUTPUT SECTION
The output stage of the TC35C25 is comprised of two
pairs of complimentary CMOS drivers operating in a push-
pull mode. Each output is capable of sinking or sourcing
nearly 500mA of peak current. They are also capable of
absorbing just as much "kick-back" current without latching.
SOFT START
A soft restart recovery rate may be selected by placing
a capacitor from SOFT START (pin 8) to ground. The
calculation for the recovery timing is approximately 60 msec/
µF.
SOFT START will mediate the start-up from under
voltage recovery, power-on, or SHUTDOWN.
SHUTDOWN
There is a minimum delay, non-latching shutdown fea-
ture on the TC35C25 PWM controller. Both outputs may be
turned off by applying a positive voltage to SHUTDOWN (pin
10). Typical shutdown threshold is 2.4V. Returning the pin
back to ground will reinitialize the soft start cycle.
OSCILLATOR SECTION
A tri-state feature has been added to accommodate
systems which require multiple controllers to be run in a
"master/slave" configuration. The timing resistor pin (RT, pin
6) may be tied to VREF to place the sync pin (SYNC, pin 3)
in a high impedance state. This will allow the chip to be
clocked from an external source.
The sync output (OSC OUT, pin 4) of the TC35C25 can
drive several sync inputs configured in this manner.
OSCILLATOR SYNCHRONIZATION
Synchronization of two TC35C25's can be done by
making one PWM Controller as the master oscillator to
synchronize the slave as follows:
6 RT
RT
TCx5C25
MASTER
5 CT GND
CT 12
OSC OUT
4
6 RT
16
VREF
3
SYNC
5 CT
TCx5C25
GND
12
SLAVE
OSCILLATOR SYNCHRONIZATION WITH
SEPARATE RC TIMER
Synchronization can also be done by having a separate
RC timing circuit on the slave oscillator that is slightly lower
frequency than the master oscillator. The sync input will not
be in a high impedance state so the number of slave
oscillators is limited. This method of synchronization is
useful when slave oscillator is located in a different location.
When a separate RC timer is used in the slave controller,
ground loop noise pickup in the oscillator is minimized.
2
3
6 RT
RT MASTER
TCx5C25
5 CT GND
OSC OUT
CT 12
4
6
RT
VREF
3
SYNC
RT TCx5C25
5 CT GND
CT 12
SLAVE
SLAVE TC > MASTER TC
4
5
6
7
8
TELCOM SEMICONDUCTOR, INC.
4-115
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| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet TC25C25.PDF ] | |
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