DataSheet.es    


PDF T7256 Data sheet ( Hoja de datos )

Número de pieza T7256
Descripción (T7234 - T7256) Compliance
Fabricantes Agere Systems 
Logotipo Agere Systems Logotipo



Hay una vista previa y un enlace de descarga de T7256 (archivo pdf) en la parte inferior de esta página.


Total 60 Páginas

No Preview Available ! T7256 Hoja de datos, Descripción, Manual

www.DataSheet4U.com
Advisory
November 1998
T7234, T7237, and T7256
Compliance with the New ETSI PSD Requirement
(Refer to the T7234, T7237, and T7256 ISDN transceiver data sheets.)
Telecommunication Standard
The European Telecommunications Standards Institute (ETSI) has identified a change in the requirement of
the power spectral density (PSD) for Basic Rate Interface ISDN.
Section A.12.4, Power Spectral Density, of ETSI TS080 states the following:
s The upper boundary of the power spectral density of the transmitted signal shall be as shown in Figure 1,
below.
s Measurements to verify compliance with this requirement are to use a noise power bandwidth of 1.0 kHz.
s Systems deployed before January 1, 2000 do not have to meet this PSD requirement but shall meet the PSD
requirements as defined in ETR 080 edition 2. It is, however, expected that these systems will also meet the
PSD requirements of TS080 edition 3. Some narrowband violations could occur and should be tolerated.
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
0.001
0.050
0.315
1.000
0.010
5.000
30.000
0.100
1.000
f (MHz)
10.000
100.000
Figure 1. Upper Boundary of Power Spectral Density from NT1 and LT
5-7388F
The existing SCNT1 family (T7234A, T7237A, and T7256A) of U-interface transceivers fully comply with this
standard.
Conformance to the above requirement has been fully verified, and test reports are available upon request.

1 page




T7256 pdf
Data Sheet
February 1998
T7234 Single-Chip NT1 (SCNT1)
Euro-LITE Transceiver
Features
s U- to S/T-interface conversion for ISDN basic rate
(2B+D) systems
— Integrated U- and S/T-interfaces
— Operates in stand-alone mode to provide U- and
S/T-interface activation, control, and mainte-
nance functions
— Automatic embedded operations channel (eoc)
processing for ANSI T1.601 systems
— Low power consumption supporting line-pow-
ered NT1 (See Table 15 on page 49, Question
and Answers section, #47 for detailed power
consumption information)
— Idle-mode support (35 mW typical)
— Board-level testability support
s U-interface
— Conforms to ANSI T1.601 standard and ETSI
ETR 080 technical report
— 2B1Q four-level line code
— Automatic ANSI maintenance functions (quiet
mode and insertion loss mode plus the MLT
function as an option for North America)
s S/T-interface
— Conforms to ANSI T1.605 standard, ITU-T I.430
recommendation, and ETSI ETS 300 012 for NT
operation
s Other
— Single +5 V (±5%) supply
— –40 °C to +85 °C
— 44-pin PLCC
Description
The Lucent Technologies Microelectronics Group
T7234 Single-Chip NT1 (SCNT1) Transceiver inte-
grated circuit provides data (2B+D) and control infor-
mation conversion between 2-wire (U-interface) and
4-wire (S/T-interface) digital subscriber loops on the
integrated services digital network (ISDN). The
T7234 conforms to the ANSI T1.601 standard and
ETSI ETR 080 technical report for the U-interface
and the ITU-T I.430 recommendation, ANSI T1.605
standard, and ETSI ETS 300 012 for the S/T-inter-
face. The single +5 V CMOS device is packaged in a
44-pin plastic leaded chip carrier (PLCC).

5 Page





T7256 arduino
Data Sheet
February 1998
T7234 Single-Chip NT1 (SCNT1) Euro-LITE Transceiver
Pin Information (continued)
Table 1. Pin Description (continued)
Pin Symbol Type*
Name/Function
25, 34, GNDA
40, 41
Analog Ground. Ground leads for analog circuitry.
26 RNR
I Receive Negative Rail for S/T-Interface. Negative input of S/T-interface analog re-
ceiver. Connect to transformer through a 10 kΩ ± 10% resistor.
27 RPR
I Receive Positive Rail for S/T-Interface. Positive input of S/T-interface analog re-
ceiver. Connect to transformer through a 10 kΩ ± 10% resistor.
28 VRCM — Common-Mode Voltage Reference for U-Interface Circuits. Connect a
0.1 µF ± 20% capacitor to GNDA (as close to the device pins as possible).
29 VRP — Positive Voltage Reference for U-Interface Circuits. Connect a 0.1 µF ± 20% ca-
pacitor to GNDA (as close to the device pins as possible).
30 VRN — Negative Voltage Reference for U-Interface Circuits. Connect a 0.1 µF ± 20% ca-
pacitor to GNDA (as close to the device pins as possible).
31 HN
I Hybrid Negative Input for U-Interface. Connect directly to negative side of
U-interface transformer.
32 LOP O Line Driver Positive Output for U-Interface. Connect to the U-interface transformer
through a 16.9 Ω ± 1% resistor.
35 LON O Line Driver Negative Output for U-Interface. Connect to the U-interface transform-
er through a 16.9 Ω ± 1% resistor.
36 HP
I Hybrid Positive Input for U-Interface. Connect directly to positive side of
U-interface transformer.
37 SDINN
I Sigma-Delta A/D Negative Input for U-Interface. Connect via an 820 pF ± 5%
capacitor to SDINP.
38 SDINP
I Sigma-Delta A/D Positive Input for U-Interface. Connect via an 820 pF ± 5%
capacitor to SDINN.
43 RESET Id Reset (Active-Low). Asynchronous Schmitt trigger input. Reset halts data transmis-
sion, clears adaptive filter coefficients, resets the U-transceiver timing recovery cir-
cuitry, resets the S/T-interface transceiver, and sets all microprocessor register bits
to their default state. During reset, the U-interface transmitter produces 0 V and the
output impedance is 135 at tip and ring. The RESET pin can be used to implement
quiet mode maintenance testing (refer to pin 2 for more description). The states of
ACTMODE, SYN8K_CTL, and AUTOACT are read upon exiting reset state (see cor-
responding pin descriptions). An internal 100 kpull-down resistor is on this pin.
RESET must be held low for 1.5 ms after power-on. Device is fully functional after an
additional 1 ms.
44 HIGHZ Iu High-Impedance Control (Active-Low). Control of the high-impedance function. An
internal 100 kpull-up resistor is on this pin. Note: This pin does not 3-state the an-
alog outputs.
0—All digital outputs enter high-impedance state.
1—No effect on device operation.
* Iu = input with internal pull-up; Id = input with internal pull-down.
Lucent Technologies Inc.
7

11 Page







PáginasTotal 60 Páginas
PDF Descargar[ Datasheet T7256.PDF ]




Hoja de datos destacado

Número de piezaDescripciónFabricantes
T7256(T7234 - T7256) ComplianceAgere Systems
Agere Systems

Número de piezaDescripciónFabricantes
SLA6805M

High Voltage 3 phase Motor Driver IC.

Sanken
Sanken
SDC1742

12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.

Analog Devices
Analog Devices


DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.


DataSheet.es    |   2020   |  Privacy Policy  |  Contacto  |  Buscar