DataSheet.es    


PDF S71WS145NX0 Data sheet ( Hoja de datos )

Número de pieza S71WS145NX0
Descripción Stacked Multi-Chip Product (MCP)
Fabricantes SPANSION 
Logotipo SPANSION Logotipo



Hay una vista previa y un enlace de descarga de S71WS145NX0 (archivo pdf) en la parte inferior de esta página.


Total 30 Páginas

No Preview Available ! S71WS145NX0 Hoja de datos, Descripción, Manual

www.DataSheet4U.com
S71WS-Nx0 Based MCPs
Stacked Multi-Chip Product (MCP)
128/256/512 Megabit (32M/16M x 16 bit) CMOS
1.8 Volt-only Simultaneous Read/Write,
Burst-mode Flash Memory with
pSRAM Type 4
Data Sheet
ADVANCE
INFORMATION
Notice to Readers: This document states the current technical specifications
regarding the Spansion product(s) described herein. Each product described
herein may be designated as Advance Information, Preliminary, or Full
Production. See Notice On Data Sheet Designations for definitions.
Publication Number S71WS-N_01 Revision A Amendment 4 Issue Date September 15, 2005
This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not
design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice.

1 page




S71WS145NX0 pdf
Advance Information
11.6.2 ACC Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
11.6.3 Low VCC Write Inhibit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
11.6.4 Write Pulse “Glitch Protection” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
11.6.5 Power-Up Write Inhibit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
12 Power Conservation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
12.1 Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
12.2 Automatic Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
12.3 Hardware RESET# Input Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
12.4 Output Disable (OE#). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
13 Secured Silicon Sector Flash Memory Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
13.1 Factory Secured SiliconSector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
13.2 Customer Secured Silicon Sector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
13.3 Secured Silicon Sector Entry/Exit Command Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
14 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
14.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
14.2 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
14.3 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
14.4 Key to Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
14.5 Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
14.6 VCC Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
14.7 DC Characteristics (CMOS Compatible) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
14.8 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
14.8.1 CLK Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
14.8.2 Synchronous/Burst Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
14.8.3 Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
14.8.4 AC Characteristics—Asynchronous Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
14.8.5 Hardware Reset (RESET#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
14.8.6 Erase/Program Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
14.8.7 Erase and Programming Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
14.8.8 BGA Ball Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
15 Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
15.1 Common Flash Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
16 Commonly Used Terms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
1.8V pSRAM Type 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
17 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
18 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
19 Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
20 Power Up and Standby Mode Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
20.1 Power Up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
20.2 Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
21 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
22 Mode Register Setting Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
22.1 Mode Register Set (MRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
22.2 Mode Register Setting Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
23 Asynchronous Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
23.1 Asynchronous 4 Page Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
23.2 Asynchronous Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
23.3 Asynchronous Write Operation in Synchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
24 Synchronous Burst Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
24.1 Synchronous Burst Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
24.2 Synchronous Burst Write Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
25 Synchronous Burst Operation Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
25.1 Clock (CLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
25.2 Latency Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
25.3 Burst Length. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
September 15, 2005 S71WS-N_01_A4
S71WS-Nx0 Based MCPs
3

5 Page





S71WS145NX0 arduino
Advance Information
Figure 31.10 Timing Waveform Of Multiple Write Cycle (Low ADV# Type).................................................................. 127
Figure 32.1 AC Output Load Circuit..................................................................................................................... 128
Figure 32.2 Timing Waveform Of Basic Burst Operation......................................................................................... 130
Figure 32.3 Timing Waveform of Burst Read Cycle (1) .......................................................................................... 131
Figure 32.4 Timing Waveform of Burst Read Cycle (2) .......................................................................................... 132
Figure 32.5 Timing Waveform of Burst Read Cycle (3) .......................................................................................... 133
Figure 32.6 Timing Waveform of Burst Write Cycle (1) .......................................................................................... 134
Figure 32.7 Timing Waveform of Burst Write Cycle (2) .......................................................................................... 135
Figure 32.8 Timing Waveform of Burst Read Stop by CS# ..................................................................................... 136
Figure 32.9 Timing Waveform of Burst Write Stop by CS# ..................................................................................... 137
Figure 32.10 Timing Waveform of Burst Read Suspend Cycle (1).............................................................................. 138
Figure 33.1 Synchronous Burst Read to Asynchronous Write (Address Latch Type) ................................................... 139
Figure 33.2 Synchronous Burst Read to Asynchronous Write (Low ADV# Type) ........................................................ 140
Figure 33.3 Asynchronous Write (Address Latch Type) to Synchronous Burst Read Timing ......................................... 141
Figure 33.4 Asynchronous Write (Low ADV# Type) to Synchronous Burst Read Timing .............................................. 142
Figure 33.5 Synchronous Burst Read to Synchronous Burst Write Timing................................................................. 143
Figure 33.6 Synchronous Burst Write to Synchronous Burst Read Timing................................................................. 144
Figure 36.1 Power Up Timing............................................................................................................................. 147
Figure 36.2 Standby Mode State Machines .......................................................................................................... 147
Figure 38.1 Mode Register Setting Timing (OE# = VIH) ......................................................................................... 151
Figure 39.1 Asynchronous 4-Page Read .............................................................................................................. 152
Figure 39.2 Asynchronous Write......................................................................................................................... 152
Figure 40.1 Synchronous Burst Read .................................................................................................................. 153
Figure 40.2 Synchronous Burst Write.................................................................................................................. 153
Figure 41.1 Latency Configuration (Read)............................................................................................................ 154
Figure 41.2 WAIT# and Read/Write Latency Control ............................................................................................. 155
Figure 42.1 PAR Mode Execution and Exit............................................................................................................ 157
Figure 47.1 PAR Mode Execution and Exit............................................................................................................ 159
Figure 47.2 Timing Waveform Of Asynchronous Read Cycle ................................................................................... 161
Figure 47.3 Timing Waveform Of Page Read Cycle................................................................................................ 162
Figure 47.4 Timing Waveform Of Write Cycle ....................................................................................................... 163
Figure 47.5 Timing Waveform of Write Cycle(2) ................................................................................................... 164
Figure 47.6 Timing Waveform Of Write Cycle (Address Latch Type) ........................................................................ 165
Figure 47.7 Timing Waveform Of Write Cycle (Low ADV# Type) ............................................................................. 166
Figure 47.8 Timing Waveform Of Write Cycle (Low ADV# Type) ............................................................................. 167
Figure 47.9 Timing Waveform Of Multiple Write Cycle (Low ADV# Type).................................................................. 168
Figure 48.1 AC Output Load Circuit..................................................................................................................... 169
Figure 48.2 Timing Waveform Of Basic Burst Operation......................................................................................... 171
Figure 48.3 Timing Waveform of Burst Read Cycle (1) .......................................................................................... 172
Figure 48.4 Timing Waveform of Burst Read Cycle (2) .......................................................................................... 173
Figure 48.5 Timing Waveform of Burst Read Cycle (3) .......................................................................................... 174
Figure 48.6 Timing Waveform of Burst Write Cycle (1) .......................................................................................... 175
Figure 48.7 Timing Waveform of Burst Write Cycle (2) .......................................................................................... 176
Figure 48.8 Timing Waveform of Burst Read Stop by CS# ..................................................................................... 177
Figure 48.9 Timing Waveform of Burst Write Stop by CS# ..................................................................................... 178
Figure 48.10 Timing Waveform of Burst Read Suspend Cycle (1).............................................................................. 179
Figure 49.1 Synchronous Burst Read to Asynchronous Write (Address Latch Type) ................................................... 180
Figure 49.2 Synchronous Burst Read to Asynchronous Write (Low ADV# Type) ........................................................ 181
Figure 49.3 Asynchronous Write (Address Latch Type) to Synchronous Burst Read Timing ......................................... 182
Figure 49.4 Asynchronous Write (Low ADV# Type) to Synchronous Burst Read Timing .............................................. 183
Figure 49.5 Synchronous Burst Read to Synchronous Burst Write Timing................................................................. 184
Figure 49.6 Synchronous Burst Write to Synchronous Burst Read Timing................................................................. 185
September 15, 2005 S71WS-N_01_A4
S71WS-Nx0 Based MCPs
9

11 Page







PáginasTotal 30 Páginas
PDF Descargar[ Datasheet S71WS145NX0.PDF ]




Hoja de datos destacado

Número de piezaDescripciónFabricantes
S71WS145NX0Stacked Multi-Chip Product (MCP)SPANSION
SPANSION

Número de piezaDescripciónFabricantes
SLA6805M

High Voltage 3 phase Motor Driver IC.

Sanken
Sanken
SDC1742

12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.

Analog Devices
Analog Devices


DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.


DataSheet.es    |   2020   |  Privacy Policy  |  Contacto  |  Buscar