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PDF S29WS512N Data sheet ( Hoja de datos )

Número de pieza S29WS512N
Descripción Migrating from the S71WS512N to the S71WS512P
Fabricantes SPANSION 
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S71WS512N to S71WS512P
Migrating from the S71WS512N to the S71WS512P
Application Note
by Daisuke Nakata
1. Introduction
Migrating from the S71WS512N to the monolithic S71WS512P is a simple process; however, the user should be aware of a few
differences between these two parts. These differences are the result of the S71WS512N using two S29WS256N die in series
while the S71WS512P uses a single S29WS512P configuration. This application note describes these differences in detail so
users currently using the S71WS512N configuration can plan ahead and include the necessary software to ensure a smooth
migration to the S71WS512P. Both software and hardware considerations are covered. Table 1.1 shows a comparison of the
key features between the two flash device cores.
Table 1.1 Comparison of Key Features
Futures
Technology
Process Rule
VCC
VIO (VCCQ)
Max Density
Configuration Register
Sector Architecture
Bank Architecture
Bank Size
Boot Option
Common Flash Interface (CFI)
Simultaneous Read/Write
Asynchronous Read Mode
Page Mode Read
Page Size
Synchronous (Burst) Read Mode
Burst Frequency
Burst Length
Single Word / Write Buffer Program
Write Buffer Size
Program Suspend / Program Resume
Sector Erase / Chip Erase
Erase Suspend / Erase Resume
Unlock Bypass / Fast Mode
Accelerated Program / Chip Erase
Sector Protection
Secured Silicon Area
S29WS256N
MirrorBit
110 nm
1.70 V to 1.95 V
=VCC
256 Mb
CR0-CR15
16 K-words Small Sector
64 K-words Large Sector
16 Bank Structure
2 Mb
Top / Bottom / Dual
Yes
Yes
Yes
Yes
4-words
Yes
54 MHz / 66 MHz / 80 MHz
8 / 16 / 32 Continuous
Yes
32-words
Yes
Yes
Yes
Yes
Yes
Hardware: WP#
Software: ASP
128-words factory locked
128-words customer lockable
S29WS512P
MirrorBit
90 nm
1.70 V to 1.95 V
=VCC
512 Mb
CR0.0 - CR0.15, CR1.0 - CR1.15
16 K-words Small Sector
64 K-words Large Sector
16 Bank Structure
4 Mb
Top / Bottom / Dual
Yes
Yes
Yes
Yes
8-words
Yes
54 MHz / 66 MHz / 80 MHz / 108 MHz
8 / 16 / 32 Continuous
Yes
32-words
Yes
Yes
Yes
Yes
Yes
Hardware: WP#
Software: ASP
128-words factory locked
128-words customer lockable
Publication Number 2xWS-N_to_WS-P_AN
Revision 01E
Issue Date October 3, 2006

1 page




S29WS512N pdf
Application Note
Table 4.2 S29WS512P Configuration Register
CR Bit
CR 0.15 Set Device Read Mode
CR 0.14 Reserved
CR 1.0
CR 0.13
CR 0.12
CR 0.11
Programmable Wait
State
CR 0.10 RDY Polarity
CR 0.9 Reserved
CR 0.8 RDY
CR 0.7 Reserved
CR 0.6 Mode of Operation
CR 0.5 Data Rate
CR 0.4 RDY Function
CR 0.3 Burst Wrap Around
CR 0.2
CR 0.1 Burst Length
CR 0.0
CR 1.15 Reserved
CR 1.14 Reserved
CR 1.13 Reserved
CR 1.12 Reserved
CR 1.11 Reserved
CR 1.10 Reserved
CR 1.9 Reserved
CR 1.8 Reserved
CR 1.7 Reserved
CR 1.6 Reserved
CR 1.5 Reserved
CR 1.3 Reserved
CR 1.2 Reserved
CR 1.1 Reserved
Function
Settings
0: Burst Read Mode
1: Asynchronous Read Mode
0: Reserved
1: Reserved (Default)
2nd 3rd 4th 5th 6th 7th 8th 9th
00000011
0
0
0
0
1
1
0
0
Initial data is valid on the 2nd (3rd, 4th...9th) rising
CLK edge after addresses are latched.
00110000
01010101
0: RDY signal active LOW
1: RDY signal active HIGH (Default)
1: Default
0: RDY active 1-clock cycle before data
1: RDY active with data
1: Default
0: Zero Hold Mode
1: Legacy Mode (Default)
0: Default
0: Default
0: No Wrap Around Burst
1: Wrap Around Burst (Default)
Continuous
(Default)
8-Word
Linear
Burst
16-Word
Linear
Burst
32-Word
Linear
Burst
0 0 01
0 1 10
0 0 10
1: Default
1: Default
1: Default
1: Default
1: Default
1: Default
1: Default
1: Default
1: Default
1: Default
1: Default
1: Default
1: Default
1: Default
October 3, 2006 2xWS-N_to_WS-P_AN_01E
S71WS512N to S71WS512P
5

5 Page





S29WS512N arduino
Application Note
Table 5.5 DC Characteristics Comparison
DC Characteristics
S29WS256N
S29WS512P
Ambient Temperature
-25°C to 85°C
-25°C to 85°C
Supply Voltage
+1.70 V to +1.95 V
+1.70 V to +1.95 V
VIL (Input Low Voltage): VCC = 1.8 V
-0.5 V / 0.4 V (Typ/Max)
-0.5 V / 0.4 V (Typ/Max)
VIH (Input High Voltage): VCC = 1.8 V
VCC - 0.4 V / VCC + 0.4 V (Typ/Max) VCC - 0.4 V / VCC + 0.4 V (Typ/Max)
VOL (Output Low Voltage): IOL = 100 µA, VCC = VCCmin = VCC 0.1 V (Max)
0.1 V (Max)
VOH (Output High Voltage): IOL =100 µA, VCC = VCCmin = VCC VCC (Min)
VCC - 0.1 V (Min)
VHH (Voltage for Accelerated Program)
8.5 V - 9.5 V (Min/Max)
8.5 V - 9.5 V (Min/Max)
VLKO (Low Vcc Lock-out Voltage)
1.4 V (Max)
1.4 V (Max)
Standby
20 mA/70 mA (Typ/Max)
20 mA/40 mA (Typ/Max)
Async. Read 54 MHz
17 mA/26 mA (Typ/Max)
20 mA/40 mA (Typ/Max)
VCC Active Current
VCC =1.70-1.95 V
Page Read
Burst Read 8-word Max-Freq.
10 mA/15 mA (Typ/Max)
80 MHz: 30 mA/66 mA (Typ/Max)
10 mA/15 mA (Typ/Max)
108 MHz: 36 mA/54 mA (Typ/Max)
Burst Read 16-word Max-Freq
80 MHz: 32 mA/60 mA (Typ/Max) 108 MHz: 32 mA/48 mA (Typ/Max)
Prog/Erase Current
24 mA/52.5 mA (Typ/Max)
20 mA/40 mA (Typ/Max)
6. AC Characteristics
Table 6.1 S29WS256N Asynchronous Read
Parameter
Description
tCE
tACC
tAVDP
tAAVDS
tAAVDH
tOE
tOEH
Access Time from CE# Low
Asynchronous Access Time
AVD# Low Time
Address Setup Time to Rising Edge of AVD#
Address Hold Time from Rising Edge of AVD#
Output Enable to Output Valid
Read
Output Enable Hold Time Toggled and Data#
Polling
tOEZ
tCAS
tPACC
Output Enable to High Z
CE# Setup Time to AVD#
Intra Page Access Time
Mode
54 MHz 66 MHz 80 MHz
— Max
80
— Max
80
— Min
8
— Min
4
— Min
7
6
— Max
13.5
— Min
0
108 MHz
Unit
ns
ns
ns
ns
ns
ns
ns
— Min
10
— ns
— Max
— Min
— Max
10
0
— ns
— ns
ns
October 3, 2006 2xWS-N_to_WS-P_AN_01E
S71WS512N to S71WS512P
11

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