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PDF CDCR83A Data sheet ( Hoja de datos )
| Número de pieza | CDCR83A | |
| Descripción | DIRECT RAMBUS CLOCK GENERATOR | |
| Fabricantes | TelCom Semiconductor | |
| Logotipo |  |
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CDCR83A
www.ti.com
DIRECT RAMBUS™ CLOCK GENERATOR
SCAS811 – AUGUST 2005
FEATURES
• 400-MHz Differential Clock Source for Direct
Rambus™ Memory Systems for an 800-MHz
Data Transfer Rate
• Fail-Safe Power Up Initialization
• Synchronizes the Clock Domains of the
Rambus Channel With an External System or
Processor Clock
• Three Power Operating Modes to Minimize
Power for Mobile and Other Power-Sensitive
Applications
• Operates From a Single 3.3-V Supply and
120 mW at 300 MHz (Typ)
• Packaged in a Shrink Small-Outline Package
(DBQ)
• Supports Frequency Multipliers: 4, 6, 8, 16/3
• No External Components Required for PLL
• Supports Independent Channel Clocking
• Spread Spectrum Clocking Tracking
Capability to Reduce EMI
• Designed for Use With TI's 133-MHz Clock
Synthesizers CDC924 and CDC921
• Cycle-Cycle Jitter Is Less Than 50 ps at
400 MHz
• Certified by Gigatest Labs to Exceed the
Rambus DRCG Validation Requirement
• Supports Industrial Temperature Range of
–40°C to 85°C
DBQ PACKAGE
(TOP VIEW)
VDDIR
REFCLK
VDDP
GNDP
GNDI
PCLKM
SYNCLKN
GNDC
VDDC
VDDIPD
STOPB
PWRDNB
1
2
3
4
5
6
7
8
9
10
11
12
24 S0
23 S1
22 VDDO
21 GNDO
20 CLK
19 NC
18 CLKB
17 GNDO
16 VDDO
15 MULT0
14 MULT1
13 S2
NC − No internal connection
DESCRIPTION
The Direct Rambus clock generator (DRCG) provides the necessary clock signals to support a Direct Rambus
memory subsystem. It includes signals to synchronize the Direct Rambus channel clock to an external system or
processor clock. It is designed to support Direct Rambus memory on a desktop, workstation, server, and mobile
PC motherboards. DRCG also provides an off-the-shelf solution for a broad range of Direct Rambus memory
applications.
The DRCG provides clock multiplication and phase alignment for a Direct Rambus memory subsystem to enable
synchronous communication between the Rambus channel and ASIC clock domains. In a Direct Rambus
memory subsystem, a system clock source provides the REFCLK and PCLK clock references to the DRCG and
memory controller, respectively. The DRCG multiplies REFCLK and drives a high-speed BUSCLK to RDRAMs
and the memory controller. Gear ratio logic in the memory controller divides the PCLK and BUSCLK frequencies
by ratios M and N such that PCLKM = SYNCLKN, where SYNCLK = BUSCLK/4. The DRCG detects the phase
difference between PCLKM and SYNCLKN and adjusts the phase of BUSCLK such that the skew between
PCLKM and SYNCLKN is minimized. This allows data to be transferred across the SYNCLK/PCLK boundary
without incurring additional latency.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DIRECT RAMBUS, Rambus are trademarks of Rambus Inc.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005, Texas Instruments Incorporated
1 page  
www.ti.com
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
VDD Supply voltage
VIH High-level input voltage (CMOS)
VIL Low-level input voltage (CMOS)
Initial phase error at phase detector inputs
(required range for phase aligner)
VIL REFCLK low-level input voltage
VIH REFCLK high-level input voltage
VIL Input signal low voltage (STOPB)
VIH Input signal high voltage (STOPB)
Input reference voltage for (REFCLK) (VDDIR)
Input reference voltage for (PCLKM and SYSCLKN) (VDDIPD)
IOH High-level output current
IOL Low-level output current
TA Operating free-air temperature
TIMING REQUIREMENTS
tc(in) Input cycle time
Input cycle-to-cycle jitter
Input duty cycle over 10,000 cycles
fmod Input frequency modulation,
Modulation index, nonlinear maximum 0.5%
Phase detector input cycle time (PCLKM and SYNCLKN)
SR Input slew rate
Input duty cycle (PCLKM and SYNCLKN)
CDCR83A
SCAS811 – AUGUST 2005
MIN
3.135
0.7 × VDD
–0.5 × tc(PD)
0.7 × VDDIR
0.7 × VDDIPD
1.235
1.235
–40
NOM
3.3
MAX
3.465
0.3 × VDD
0.5 × tc(PD)
UNIT
V
V
V
V
0.3 × VDDIR
0.3 × VDDIPD
3.465
3.465
–16
16
85
V
V
V
V
V
V
mA
mA
°C
MIN
10
40%
30
30
1
25%
MAX
40
250
60%
33
0.6%
100
4
75%
UNIT
ns
ps
kHz
ns
V/ns
5
5 Page 
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet CDCR83A.PDF ] | |
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