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PDF 82572EI Data sheet ( Hoja de datos )

Número de pieza 82572EI
Descripción (82571EB / 82572EI Gigabit Ethernet Controller
Fabricantes Intel Corporation 
Logotipo Intel Corporation Logotipo



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82571EB/82572EI Gigabit Ethernet
Controller
Networking Silicon
Product Datasheet
Revision 1.2
August 2006

1 page




82572EI pdf
82571EB/82572 Gigabit Ethernet Controller
5.0 Package and Pinout Information..................................................................................................35
5.1 Package Information..........................................................................................................35
5.2 Thermal Specification .......................................................................................................37
5.3 Pinout Information.............................................................................................................37
5.4 Visual Pin Assignments.....................................................................................................50
Product Datasheet
v

5 Page





82572EI arduino
2.0
2.1
2.2
82571EB/82572EI Gigabit Ethernet Controller
Features of the 82571EB/82572EI Gigabit Ethernet
Controller
PCI Express Features
Features
Uses x4 PCI Express interface on MCH device
Peak bandwidth 2 GB/s in each direction per PCI Express
lane
PCI Express Power Management
High bandwidth density per pin
Benefits
• Bus sharing not required
• Low latency path to memory
• Relieves congestion for IO devices
• Supports Gigabit Ethernet at full wire speed
• Compatible extensions to PCI power management and
ACPI
• PE_WAKE_n available for wakeup event
• Less congested board routing
MAC-Specific Features
Features
Benefits
Optimized transmit and receive queues
• Network packets handled without waiting or buffer
overflow.
• Control over the transmissions of pause frames through
IEEE 802.3x compliant flow control support with software
software or hardware triggering
controllable pause times and threshold values
• Frame loss reduced from receive overruns
Caches up to 64 packet descriptors (per queue)
• Efficient use of PCI Express bandwidth
Separate transmit queue per port
• Efficient packet prioritization
Programmable host memory receive buffers (256 Bytes to
16 KBytes) and cache line size (64 Bytes to 128 Bytes)
• Efficient use of PCI Express bandwidth
Wide, pipelined internal data path architecture
• Low latency data handling
• Superior DMA transfer rate performance
Dual 48 KByte configurable Transmit and Receive FIFO
buffers
• No external FIFO memory requirements
• FIFO size adjustable to application
Descriptor ring management hardware for transmit and
receive
• Simple software programming model
Optimized descriptor fetching and write-back mechanisms
Efficient system memory and use of PCI Express
bandwidth
Mechanism available for reducing interrupts generated by
transmit and receive operations
• Maximizes system performance and throughput
Supports transmission and reception of packets up to 9 kB • Enables jumbo frames
Product Datasheet
5

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