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Número de pieza | S71GL128NB0 | |
Descripción | (S71GLxxxNB0) Stacked Multi-chip Product (MCP) | |
Fabricantes | SPANSION | |
Logotipo | ||
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S71GL512NB0/S71GL256NB0/
S71GL128NB0
Stacked Multi-chip Product (MCP)
512/256/128 Megabit (32/16/8 M x 16-bit) CMOS 3.0 Volt-only
MirrorBitTM Page-mode Flash Memory with
32 Megabit (2M x 16-bit) pSRAM
Distinctive Characteristics
ADVANCE
INFORMATION
MCP Features
Power supply voltage of 2.7 to 3.1V
High Performance
90 ns access time (S71GL128N, S71GL256N)
100 ns access time (S71GL512N)
25 ns page read times
Packages:
— 9.0 x 12.0 mm x 1.2 mm FBGA (TLD084) (S71GL512N)
— 8.0 x 11.6 mm x 1.2 mm FBGA (TLA084) (S71GL128N, S71GL256N)
Operating Temperature
— -25°C to +85°C (Wireless)
— -40°C to +85°C (Industrial)
General Description
The S71GL Series is a product line of stacked Multi-chip Product (MCP) packages
and consists of
One Flash memory die
one pSRAM
The products covered by this document are listed in the table below. For details
about their specifications, please refer to the individual constituent datasheets
for further details.
pSRAM Density
128 Mb
64 Mb
32 Mb
16 Mb
512 Mb
Flash Memory Density
256 Mb
128 Mb
S71GL512NB0 S71GL256NB0 S71GL128NB0
Publication Number S71GL512_256_128NB0_00 Revision A Amendment 1 Issue Date December 7, 2004
This document contains information on a product under development at Spansion LLC. The information is intended to help you evaluate this product. Spansion LLC
reserves the right to change or discontinue work on this proposed product without notice.
1 page Advance Information
MCP Block Diagram (128Mb Flash + 32Mb pSRAM)
VCCf
Flash-only Address
Shared Address
WP#/ACC
CE#F1
OE#
WE#
RESET#
2
21
VCC VID
DQ15 to DQ0
WP#/ACC
CE#
Flash
OE#
WE#
RESET# RY/BY#
16
VCCs
21 VCC VCCQ
I/O15 to I/O0
UB#s
LB#s
CE2s
CE1#s
WE#
OE#
UB#
LB#
CE2s
CE1#s
pSRAM
VSSQ
MCP Block Diagram (256Mb Flash + 32Mb pSRAM)
16
VCCf
Flash-only Address
Shared Address
WP#/ACC
CE#F1
OE#
WE#
RESET#
VCCs
UB#s
LB#s
CE2s
CE1#s
3
21
VCC VID
DQ15 to DQ0
WP#/ACC
CE#
Flash
OE#
WE#
RESET# RY/BY#
16
21 VCC VCCQ
I/O15 to I/O0
WE#
OE#
UB#
LB#
CE2s
CE1#s
pSRAM
VSSQ
16
DQ15 to DQ0
RY/BY#
VSS
DQ15 to DQ0
RY/BY#
VSS
December 7, 2004 S71GL512_256_128NB0_00_A1
5
5 Page Advance Information
Input/Output Descriptions
A24-A0
A23-A0
A22-A0
DQ15-DQ0
OE#
=
=
=
=
=
WE#
VSS
NC
RESET#
=
=
=
=
WP#/ACC
=
CE1#s, CE2s
CE#f1
VCCf
VCCs
UB#s
LB#s
RFU
RY/BY#
=
=
=
=
=
=
=
=
Logic Symbol
25 Address inputs (512 Mb)
24 Address inputs (256 Mb)
23 Address inputs (128 Mb)
Data input/output
Output Enable input. Asynchronous relative to CLK
for the Burst mode.
Write Enable input.
Ground
No Connect; not connected internally
Hardware reset input. Low = device resets and
returns to reading array data
Hardware write protect input / programming
acceleration input.
Chip-enable input for pSRAM.
Chip-enable input for Flash 1.
Flash 3.0 Volt-only single power supply.
pSRAM Power Supply.
Upper Byte Control (pSRAM).
Lower Byte Control (pSRAM).
Reserved for future use.
Ready/Busy output.
Max+1
AMax*–A0
CE1#s
CE2s
OE#
WE#
WP#/ACC
WE#
RESET#
UB#
LB#
CE#f1
DQ15–DQ0
RY/BY#
16
*Max = A24
December 7, 2004 S71GL512_256_128NB0_00_A1
11
11 Page |
Páginas | Total 30 Páginas | |
PDF Descargar | [ Datasheet S71GL128NB0.PDF ] |
Número de pieza | Descripción | Fabricantes |
S71GL128NB0 | (S71GLxxxNB0) Stacked Multi-chip Product (MCP) | SPANSION |
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