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PDF MAX1186 Data sheet ( Hoja de datos )
| Número de pieza | MAX1186 | |
| Descripción | Low-Power ADC | |
| Fabricantes | Maxim Integrated Products | |
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19-2263; Rev 0; 12/01
Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
General Description
The MAX1186 is a 3V, dual 10-bit analog-to-digital con-
verter (ADC) featuring fully-differential wideband track-
and-hold (T/H) inputs, driving two pipelined, nine-stage
ADCs. The MAX1186 is optimized for low-power, high
dynamic performance applications in imaging, instru-
mentation, and digital communication applications. This
ADC operates from a single 2.7V to 3.6V supply, con-
suming only 105mW while delivering a typical signal-to-
noise ratio (SNR) of 59.4dB at an input frequency of
20MHz and a sampling rate of 40Msps. Digital outputs
A and B are updated alternating on the rising (CHA)
and the falling (CHB) edge of the clock. The T/H driven
input stages incorporate 400MHz (-3dB) input ampli-
fiers. The converters may also be operated with single-
ended inputs. In addition to low operating power, the
MAX1186 features a 2.8mA sleep mode as well as a
1µA power-down mode to conserve power during idle
periods.
An internal 2.048V precision bandgap reference sets
the full-scale range of the ADCs. A flexible reference
structure allows the use of this internal or an externally
derived reference, if desired for applications requiring
increased accuracy or a different input voltage range.
The MAX1186 features parallel, multiplexed, CMOS-
compatible three-state outputs. The digital output for-
mat can be set to two’s complement or straight offset
binary through a single control pin. The device provides
for a separate output power supply of 1.7V to 3.6V for
flexible interfacing. The MAX1186 is available in a
7mm x 7mm, 48-pin TQFP-EP package, and is speci-
fied for the extended industrial (-40°C to +85°C) tem-
perature range.
Pin-compatible, nonmultiplexed, high-speed versions of
the MAX1186 are also available. Please refer to the
MAX1180 data sheet for 105Msps, the MAX1181 data
sheet for 80Msps, the MAX1182 data sheet for 65Msps,
the MAX1183 data sheet for 40Msps, and the MAX1184
data sheet for 20Msps. For a pin-compatible lower
speed version (20Msps) of the MAX1186, please refer
to the MAX1185 data sheet.
Applications
High-Resolution Imaging
I/Q Channel Digitization
Multichannel IF Sampling
Instrumentation
Video Application
Ultrasound
Features
o Single 3V Operation
o Excellent Dynamic Performance:
59.4dB SNR at fIN = 20MHz
72dBc SFDR at fIN = 20MHz
o Low Power:
35mA (Normal Operation)
2.8mA (Sleep Mode)
1µA (Shutdown Mode)
o 0.02dB Gain and 0.25° Phase Matching
o Wide ±1VP-P Differential Analog Input Voltage
Range
o 400MHz, -3dB Input Bandwidth
o On-Chip 2.048V Precision Bandgap Reference
o Single 10-Bit Bus for Multiplexed, Digital Outputs
o User-Selectable Output Format–Two’s
Complement or Offset Binary
o 48-Pin TQFP Package with Exposed Paddle For
Improved Thermal Dissipation
Ordering Information
PART
MAX1186ECM
TEMP RANGE
-40°C to +85°C
PIN-PACKAGE
48 TQFP-EP
Functional Diagram appears at end of data sheet.
Pin Configuration
COM 1
VDD 2
GND 3
INA+ 4
INA- 5
VDD 6
GND 7
INB- 8
INB+ 9
GND 10
VDD 11
CLK 12
MAX1186
36 D1A/B
35 D0A/B
34 OGND
33 OVDD
32 OVDD
31 OGND
30 A/B
29 N.C.
28 N.C.
27 N.C.
26 N.C.
25 N.C.
48 TQFP-EP
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page  
Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3V, OVDD = 2.5V, 0.1µF and 1µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a
10kΩ resistor, VIN = 2VP-P (differential w.r.t. COM), CL = 10pF at digital outputs (Note 5), fCLK = 40MHz,
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
POWER REQUIREMENTS
Analog Supply Voltage Range
Output Supply Voltage Range
Analog Supply Current
VDD
OVDD
IVDD
Operating, fINA or B = 20MHz at -0.5dB FS
Sleep mode
Shutdown, clock idle, PD = OE = OVDD
2.7 3.0 3.6
V
1.7 2.5 3.6
V
35 50
mA
2.8
1 15 µA
Output Supply Current
Power Dissipation
Power-Supply Rejection Ratio
IOVDD
PDISS
PSRR
Operating, CL = 15pF, fINA or B = 20MHz at
-0.5dB FS
Sleep mode
Shutdown, clock idle, PD = OE = OVDD
Operating, fINA or B = 20MHz at -0.5dB FS
Sleep mode
Shutdown, clock idle, PD = OE = OVDD
Offset
Gain
4
100
2
105
8.4
3
±0.2
±0.1
mA
µA
10
150
mW
45 µW
mV/V
%/V
TIMING CHARACTERISTICS
CLK Rise to CHA Output Data
Valid
tDOA Figure 3 (Note 3)
5 8 ns
CLK Fall to CHB Output Data
Valid
tDOB Figure 3 (Note 3)
5 8 ns
Clock Rise/Fall to A/B Rise/Fall
Time
tDA/B
6 ns
Output Enable Time
Output Disable Time
CLK Pulse Width High
CLK Pulse Width Low
Wake-Up Time
tENABLE
tDISABLE
tCH
tCL
tWAKE
Figure 4
Figure 4
Figure 3, clock period: 25ns
Figure 3, clock period: 25ns
Wake-up from sleep mode (Note 4)
Wake-up from shutdown (Note 4)
10
1.5
12.5 ±3.8
12.5 ±3.8
0.41
1.5
ns
ns
ns
ns
µs
CHANNEL-TO-CHANNEL MATCHING
Crosstalk
Gain Matching
Phase Matching
fINA or B = 20MHz at -0.5dB FS
fINA or B = 20MHz at -0.5dB FS
fINA or B = 20MHz at -0.5dB FS
-70
0.02
0.25
dB
±0.2 dB
degrees
Note 1: SNR, SINAD, THD, SFDR, and HD3 are based on an analog input voltage of -0.5dB FS referenced to a 1.024V full-scale
input voltage range.
Note 2: Intermodulation distortion is the total power of the intermodulation products relative to the individual carrier. This number is
6dB or better, if referenced to the two-tone envelope.
Note 3: Digital outputs settle to VIH and VIL. Parameter guaranteed by design.
Note 4: With REFIN driven externally, REFP, COM, and REFN are left floating while powered down.
Note 5: Equivalent dynamic performance is obtainable over full OVDD range with reduced CL.
_______________________________________________________________________________________ 5
5 Page 
Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
Detailed Description
The MAX1186 uses a nine-stage, fully-differential,
pipelined architecture (Figure 1) that allows for high-
speed conversion while minimizing power consumption.
Samples taken at the inputs move progressively through
the pipeline stages every one-half clock cycle. Including
the delay through the output latch, the total clock-cycle
latency is five clock cycles.
1.5-bit (2-comparator) flash ADCs convert the held input
voltages into a digital code. The digital-to-analog con-
verters (DACs) convert the digitized results back into
analog voltages, which are then subtracted from the
original held input signals. The resulting error signals
are then multiplied by two and the residues are passed
along to the next pipeline stages, where the process is
repeated until the signals have been processed by all
nine stages. Digital error correction compensates for
ADC comparator offsets in each of these pipeline
stages and ensures no missing codes.
Both input channels are sampled on the rising edge of
the clock and the resulting data is multiplexed at the
output. CHA data is updated on the rising edge (5 clock
cycles later) and CHB data is updated on the falling
edge (5.5 clock cycles later) of the clock signal. The A/B
indicator follows the clock signal with a typical delay
time of 6ns and remains high when CHA data is updat-
ed and low when CHB data is updated.
Input Track-and-Hold (T/H) Circuits
Figure 2 displays a simplified functional diagram of the
input track-and-hold (T/H) circuits in both track- and hold-
mode. In track mode, switches S1, S2a, S2b, S4a, S4b,
S5a, and S5b are closed. The fully-differential circuits
sample the input signals onto the two capacitors (C2a
and C2b) through switches S4a and S4b. S2a and S2b
set the common mode for the amplifier input, and open
simultaneously with S1, sampling the input waveform.
Switches S4a and S4b are then opened before switches
S3a and S3b connect capacitors C1a and C1b to the out-
put of the amplifier and switch S4c is closed. The result-
ing differential voltages are held on capacitors C2a and
C2b. The amplifiers are used to charge capacitors C1a
and C1b to the same values originally held on C2a and
C2b. These values are then presented to the first stage
quantizers and isolate the pipelines from the fast-chang-
ing inputs. The wide input bandwidth T/H amplifiers allow
the MAX1186 to track and sample/hold analog inputs of
high frequencies (> Nyquist). Both ADC inputs (INA+,
INB+, INA-, and INB-) can be driven either differentially or
single-ended. Match the impedance of INA+ and INA-,
as well as INB+ and INB-, and set the common-mode
voltage to midsupply (VDD/2) for optimum performance.
VIN T/H Σ x2 VOUT
VIN T/H Σ x2 VOUT
FLASH
ADC
DAC
1.5 BITS
STAGE 1
STAGE 2
STAGE 8
2-BIT FLASH
ADC
STAGE 9
FLASH
ADC
DAC
1.5 BITS
STAGE 1
STAGE 2
STAGE 8
2-BIT FLASH
ADC
STAGE 9
T/H
VINA
DIGITAL CORRECTION LOGIC
10
Figure 1. Pipelined Architecture—Stage Blocks
T/H
VINB
OUTPUT
MULTIPLEXER
10
D0A/B–D9A/B
DIGITAL CORRECTION LOGIC
10
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet MAX1186.PDF ] | |
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