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PDF ADV7343 Data sheet ( Hoja de datos )
| Número de pieza | ADV7343 | |
| Descripción | (ADV7342 / ADV7343) Multiformat Video Encoder | |
| Fabricantes | Analog Devices | |
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Data Sheet
FEATURES
74.25 MHz 16-/24-bit high definition input support
Compliant with SMPTE 274M (1080i), 296M (720p),
and 240M (1035i)
Six 11-bit, 297 MHz video DACs
16× (216 MHz) DAC oversampling for SD
8× (216 MHz) DAC oversampling for ED
4× (297 MHz) DAC oversampling for HD
37 mA maximum DAC output current
NTSC M, PAL B/D/G/H/I/M/N, PAL 60 support
NTSC and PAL square pixel operation (24.54 MHz/29.5 MHz)
Multiformat video input support
4:2:2 YCrCb (SD, ED, and HD), 4:4:4 YCrCb (ED and HD), and
4:4:4 RGB (SD, ED, and HD)
Multiformat video output support
Composite (CVBS) and S-Video (Y-C)
Component YPrPb (SD, ED, and HD)
Component RGB (SD, ED, and HD)
Macrovision Rev 7.1.L1 (SD) and Rev 1.2 (ED) compliant
Simultaneous SD and ED/HD operation
EIA/CEA-861B compliance support
Copy generation management system (CGMS)
Closed captioning and wide screen signaling (WSS)
Integrated subcarrier locking to external video source
Complete on-chip video timing generator
On-chip test pattern generation
On-board voltage reference (optional external input)
Programmable features
Luma and chroma filter responses
Vertical blanking interval (VBI)
Subcarrier frequency (FSC) and phase
Luma delay
High definition (HD) programmable features
(720p/1080i/1035i)
4× oversampling (297 MHz)
Internal test pattern generator
Fully programmable YCrCb to RGB matrix
Gamma correction
Programmable adaptive filter control
Programmable sharpness filter control
CGMS (720p/1080i) and CGMS Type B (720p/1080i)
Undershoot limiter
Dual data rate (DDR) input support
Multiformat Video Encoder
Six, 11-Bit, 297 MHz DACs
ADV7342/ADV7343
Enhanced definition(ED) programmable features
(525p/625p)
8× oversampling (216 MHz output)
Internal test pattern generator
Black bar, hatch, flat field/frame
Individual Y and PrPb output delay
Gamma correction
Programmable adaptive filter control
Fully programmable YCrCb to RGB matrix
Undershoot limiter
Macrovision Rev 1.2 (525p/625p) (ADV7342 only)
CGMS (525p/625p) and CGMS Type B (525p)
Dual data rate (DDR) input support
Standard definition (SD) programmable features
16× oversampling (216 MHz)
Internal test pattern generator
Color and black bar
Controlled edge rates for start and end of active video
Individual Y and PrPb output delay
Undershoot limiter
Gamma correction
Digital noise reduction (DNR)
Multiple chroma and luma filters
Luma-SSAF filter with programmable gain/attenuation
PrPb SSAF
Separate pedestal control on component and
composite/S-Video output
VCR FF/RW sync mode
Macrovision Rev 7.1.L1 (ADV7342 only)
Copy generation management system (CGMS)
Wide screen signaling
Closed captioning
Serial MPU interface with I2C compatibility
3.3 V analog operation, 1.8 V digital operation, and 1.8 V or
3.3 V I/O operation
Temperature range: −40°C to +85°C
Qualified for automotive applications
APPLICATIONS
DVD recorders and players
High definition Blu-ray DVD players
Rev. E
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2006–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
GENERAL DESCRIPTION
The ADV7342/ADV7343 are high speed, digital-to-analog
video encoders in a 64-lead LQFP package. Six high speed,
3.3 V, 11-bit video DACs provide support for composite
(CVBS), S-Video (Y-C), and component (YPrPb/RGB) analog
outputs in standard definition (SD), enhanced definition (ED),
or high definition (HD) video formats.
The ADV7342/ADV7343 have a 24-bit pixel input port that can
be configured in a variety of ways. SD video formats are sup-
ported over an SDR interface, and ED/HD video formats are
supported over SDR and DDR interfaces. Pixel data can be
supplied in either the YCrCb or RGB color spaces.
The parts also support embedded EAV/SAV timing codes,
external video synchronization signals, and I2C® communication
protocol.
In addition, simultaneous SD and ED/HD input and output are
supported. Full-drive DACs ensure that external output buffering
is not required, while 216 MHz (SD and ED) and 297 MHz
(HD) oversampling ensures that external output filtering is not
required.
Cable detection and DAC autopower-down features keep power
consumption to a minimum.
Table 1 lists the video standards directly supported by the
ADV7342/ADV7343.
ADV7342/ADV7343
Table 1. Standards Directly Supported by the ADV7342/
ADV7343
Active
Frame
Resolution I/P1 Rate (Hz)
Clock Input
(MHz)
Standard
720 × 240 P 59.94
27
720 × 288 P 50
27
720 × 480 I
29.97
27
ITU-R
BT.601/656
720 × 576 I
25
27
ITU-R
BT.601/656
640 × 480 I
29.97
24.54
NTSC Square
Pixel
768 × 576 I
25
29.5 PAL Square
Pixel
720 × 483 P 59.94
27
SMPTE 293M
720 × 483 P 59.94
27
BTA T-1004
720 × 483 P 59.94
27
ITU-R BT.1358
720 × 576 P 50
27
ITU-R BT.1358
720 × 483 P 59.94
27
ITU-R BT.1362
720 × 576 P 50
27
ITU-R BT.1362
1920 × 1035 I
30
74.25
SMPTE 240M
1920 × 1035 I
29.97
74.1758
SMPTE 240M
1280 × 720 P
60, 50, 30, 74.25
25, 24
SMPTE 296M
1280 × 720 P
23.97,
74.1758
59.94, 29.97
SMPTE 296M
1920 × 1080 I
30, 25
74.25
SMPTE 274M
1920 × 1080 I
29.97
74.1758
SMPTE 274M
1920 × 1080 P 30, 25, 24 74.25
SMPTE 274M
1920 × 1080 P 23.98, 29.97 74.1758
SMPTE 274M
1920 × 1080 P 24
74.25
ITU-R BT.709-5
1 I = interlaced, P = progressive.
Rev. E | Page 5 of 106
5 Page 
Data Sheet
ADV7342/ADV7343
MPU PORT TIMING SPECIFICATIONS
VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, VDD_IO = 1.71 V to 3.63 V.
All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted.
Table 10.
Parameter
MPU PORT, I2C MODE1
SCL Frequency
SCL High Pulse Width, t1
SCL Low Pulse Width, t2
Hold Time (Start Condition), t3
Setup Time (Start Condition), t4
Data Setup Time, t5
SDA, SCL Rise Time, t6
SDA, SCL Fall Time, t7
Setup Time (Stop Condition), t8
Conditions
See Figure 19
Min Typ Max
0 400
0.6
1.3
0.6
0.6
100
300
300
0.6
1 Guaranteed by characterization.
POWER SPECIFICATIONS
VDD = 1.8 V, PVDD = 1.8 V, VAA = 3.3 V, VDD_IO = 3.3 V, TA = +25°C.
Table 11.
Parameter
NORMAL POWER MODE1, 2
IDD3
IDD_IO
IAA5
IPLL
SLEEP MODE
IDD
IAA
IDD_IO
IPLL
Conditions
Min Typ Max
SD only (16× oversampling)
ED only (8× oversampling)4
HD only (4× oversampling)4
SD (16× oversampling) and ED (8× oversampling)
SD (16× oversampling) and HD (4× oversampling)
Three DACs enabled (ED/HD only)
Six DACs enabled (SD only and simultaneous modes )
SD only, ED only, or HD only modes
Simultaneous modes
90
65
91
95
122
1
124
140
5
10
5
0.3
0.2
0.1
1 RSET1 = 510 Ω (DAC 1, DAC 2, and DAC 3 operating in full-drive mode). RSET2 = 4.12 kΩ (DAC 4, DAC 5, and DAC 6 operating in low drive mode).
2 75% color bar test pattern applied to pixel data pins.
3 IDD is the continuous current required to drive the digital core.
4 Applicable to both single data rate (SDR) and dual data rate (DDR) input modes.
5 IAA is the total current required to supply all DACs.
Unit
kHz
µs
µs
µs
µs
ns
ns
ns
µs
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
µA
µA
µA
µA
Rev. E | Page 11 of 106
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ADV7343.PDF ] | |
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