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PDF PDU15F Data sheet ( Hoja de datos )
| Número de pieza | PDU15F | |
| Descripción | 5-BIT PROGRAMMABLE DELAY LINE | |
| Fabricantes | Data Delay Devices | |
| Logotipo |  |
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5-BIT PROGRAMMABLE
DELAY LINE
(SERIES PDU15F)
PDU15F
data
delay
3
®
devices, inc.
FEATURES
• Digitally programmable in 32 delay steps
• Monotonic delay-versus-address variation
• Two separate outputs: inverting & non-inverting
• Precise and stable delays
• Input & outputs fully TTL interfaced & buffered
• 10 T2L fan-out capability
• Fits standard 24-pin DIP socket
• Auto-insertable
OUT/
OUT
EN/
GND
N/C
IN
N/C
GND
N/C
N/C
EN/
GND
PACKAGES
1 24
2 23
3 22
4 21
5 20
6 19
7 18
8 17
9 16
10 15
11 14
12 13
VCC
A0
A1
A2
VCC
N/C
N/C
N/C
VCC
A3
A4
N/C
PDU15F-xx
DIP
PDU15F-xxA4
Gull-Wing
PDU15F-xxB4
J-Lead
PDU15F-xxM
Military DIP
PDU15F-xxMC4
Military Gull-Wing
FUNCTIONAL DESCRIPTION
PIN DESCRIPTIONS
The PDU15F-series device is a 5-bit digitally programmable delay line.
IN Delay Line Input
The delay, TDA, from the input pin (IN) to the output pins (OUT, OUT/)
depends on the address code (A4-A0) according to the following formula:
OUT Non-inverted Output
OUT/ Inverted Output
A0-A4 Address Bits
TDA = TD0 + TINC * A
EN/ Output Enable
VCC +5 Volts
where A is the address code, TINC is the incremental delay of the device,
GND Ground
and TD0 is the inherent delay of the device. The incremental delay is
specified by the dash number of the device and can range from 0.5ns through 20ns, inclusively. The
enable pins (EN/) are held LOW during normal operation. These pins must always be in the same state
and may be tied together externally. When these signals are brought HIGH, OUT and OUT/ are forced
into LOW and HIGH states, respectively. The address is not latched and must remain asserted during
normal operation.
SERIES SPECIFICATIONS
• Total programmed delay tolerance: 5% or 1ns,
whichever is greater
• Inherent delay (TD0): 9ns typical (OUT)
8ns typical (OUT/)
• Setup time and propagation delay:
Address to input setup (TAIS): 5ns
Disable to output delay (TDISO): 6ns typ. (OUT)
• Operating temperature: 0° to 70° C
• Temperature coefficient: 100PPM/°C (excludes TD0)
• Supply voltage VCC: 5VDC ± 5%
• Supply current: ICCH = 74ma
ICCL = 30ma
• Minimum pulse width: 10% of total delay
©1997 Data Delay Devices
DASH NUMBER SPECIFICATIONS
Part
Number
PDU15F-.5
PDU15F-1
PDU15F-2
PDU15F-3
PDU15F-4
PDU15F-5
PDU15F-6
PDU15F-8
PDU15F-10
PDU15F-12
PDU15F-15
PDU15F-20
Incremental Delay
Per Step (ns)
.5 ± .3
1 ± .5
2 ± .5
3 ± 1.0
4 ± 1.0
5 ± 1.0
6 ± 1.0
8 ± 1.0
10 ± 1.5
12 ± 1.5
15 ± 1.5
20 ± 2.0
Total Delay
Change (ns)
15.5 ± 1.0
31 ± 1.6
62 ± 3.1
93 ± 4.7
124 ± 6.2
155 ± 7.8
186 ± 9.3
248 ± 12.4
310 ± 15.5
372 ± 18.6
465 ± 23.3
620 ± 31.0
NOTE: Any dash number between .5 and 20 not
shown is also available.
Doc #97003
1/13/97
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
1 page  
DELAY LINE AUTOMATED TESTING
PDU15F
TEST CONDITIONS
INPUT:
Ambient Temperature: 25oC ± 3oC
Supply Voltage (Vcc): 5.0V ± 0.1V
Input Pulse:
High = 3.0V ± 0.1V
Low = 0.0V ± 0.1V
Source Impedance: 50Ω Max.
Rise/Fall Time:
3.0 ns Max. (measured
between 0.6V and 2.4V )
Pulse Width:
PWIN = 1.5 x Total Delay
Period:
PERIN = 4.5 x Total Delay
OUTPUT:
Load:
Cload:
Threshold:
1 FAST-TTL Gate
5pf ± 10%
1.5V (Rising & Falling)
NOTE: The above conditions are for test only and do not in any way restrict the operation of the device.
COMPUTER
SYSTEM
PRINTER
PULSE
GENERATOR
OUT
TRIG
IN DEVICE UNDER OUT
TEST (DUT)
REF
IN
TRIG
TIME INTERVAL
COUNTER
Test Setup
INPUT
SIGNAL
OUTPUT
SIGNAL
TRISE
PWIN
PERIN
TFALL
2.4V VIH 2.4V
1.5V
1.5V
0.6V
0.6V
VIL
TDAR
TDAF
1.5V
VOH
1.5V
Timing Diagram For Testing
VOL
Doc #97003
1/13/97
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
5
5 Page | ||
| Páginas | Total 5 Páginas | |
| PDF Descargar | [ Datasheet PDU15F.PDF ] | |
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