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PDF PDU13F Data sheet ( Hoja de datos )
| Número de pieza | PDU13F | |
| Descripción | 3-BIT PROGRAMMABLE DELAY LINE | |
| Fabricantes | Data Delay Devices | |
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3-BIT PROGRAMMABLE
DELAY LINE
(SERIES PDU13F)
PDU13F
ddaeltaay 3
devices, inc.
FEATURES
• Digitally programmable in 8 delay steps
• Monotonic delay-versus-address variation
• Two separate outputs: inverting & non-inverting
• Precise and stable delays
• Input & outputs fully TTL interfaced & buffered
• 10 T2L fan-out capability
• Fits standard 14-pin DIP socket
• Auto-insertable
PACKAGES
IN 1 14 VCC
N/C 2 13 N/C
N/C 3 12 N/C
OUT 4 11 N/C
OUT/ 5 10 A0
EN/ 6 9 A1
GND 7 8 A2
PDU13F-xx DIP
PDU13F-xxA2 Gull-Wing
PDU13F-xxB2 J-Lead
PDU13F-xxM Military DIP
IN 1 16 VCC
N/C 2 15 N/C
N/C 3 14 N/C
N/C 4 13 N/C
OUT 5 12 A0
OUT/ 6 11 A1
EN/ 7 10 A2
GND 8 9 N/C
PDU13F-xxMC3
Military Gull-Wing
FUNCTIONAL DESCRIPTION
PIN DESCRIPTIONS
The PDU13F-series device is a 3-bit digitally programmable delay line.
The delay, TDA, from the input pin (IN) to the output pins (OUT, OUT/)
depends on the address code (A2-A0) according to the following formula:
IN Delay Line Input
OUT Non-inverted Output
OUT/ Inverted Output
TDA = TD0 + TINC * A
A2 Address Bit 2
A1 Address Bit 1
where A is the address code, TINC is the incremental delay of the device,
and TD0 is the inherent delay of the device. The incremental delay is
specified by the dash number of the device and can range from 0.5ns
through 50ns, inclusively. The enable pin (EN/) is held LOW during
A0
EN/
VCC
GND
Address Bit 0
Output Enable
+5 Volts
Ground
normal operation. When this signal is brought HIGH, OUT and OUT/ are forced into LOW and HIGH
states, respectively. The address is not latched and must remain asserted during normal operation.
SERIES SPECIFICATIONS
• Total programmed delay tolerance: 5% or 1ns,
whichever is greater
• Inherent delay (TD0): 6ns typical (OUT)
5.5ns typical (OUT/)
• Setup time and propagation delay:
Address to input setup (TAIS): 6ns
Disable to output delay (TDISO): 6ns typ. (OUT)
• Operating temperature: 0° to 70° C
• Temperature coefficient: 100PPM/°C (excludes TD0)
• Supply voltage VCC: 5VDC ± 5%
• Supply current: ICCH = 45ma
ICCL = 20ma
• Minimum pulse width: 20% of total delay
DASH NUMBER SPECIFICATIONS
Part
Number
PDU13F-.5
PDU13F-1
PDU13F-2
PDU13F-3
PDU13F-5
PDU13F-10
PDU13F-15
PDU13F-20
PDU13F-40
PDU13F-50
Incremental Delay
Per Step (ns)
.5 ± .3
1 ± .4
2 ± .4
3 ± .5
5 ± .6
10 ± 1.0
15 ± 1.3
20 ± 1.5
40 ± 2.0
50 ± 2.5
Total Delay
Change (ns)
3.5 ± 1.0
7 ± 1.0
14 ± 1.0
21 ± 1.1
35 ± 1.8
70 ± 3.5
105 ± 5.3
140 ± 7.0
280 ± 14.0
350 ± 17.5
NOTE: Any dash number between .5 and 50 not
shown is also available.
2004 Data Delay Devices
Doc #97001
3/25/04
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
1 page  
DELAY LINE AUTOMATED TESTING
PDU13F
TEST CONDITIONS
INPUT:
Ambient Temperature: 25oC ± 3oC
Supply Voltage (Vcc): 5.0V ± 0.1V
Input Pulse:
High = 3.0V ± 0.1V
Low = 0.0V ± 0.1V
Source Impedance: 50Ω Max.
Rise/Fall Time:
3.0 ns Max. (measured
between 0.6V and 2.4V )
Pulse Width:
PWIN = 1.5 x Total Delay
Period:
PERIN = 4.5 x Total Delay
OUTPUT:
Load:
Cload:
Threshold:
1 FAST-TTL Gate
5pf ± 10%
1.5V (Rising & Falling)
NOTE: The above conditions are for test only and do not in any way restrict the operation of the device.
COMPUTER
SYSTEM
PRINTER
PULSE
GENERATOR
OUT
TRIG
IN DEVICE UNDER OUT
TEST (DUT)
REF
IN
TRIG
TIME INTERVAL
COUNTER
Test Setup
INPUT
SIGNAL
OUTPUT
SIGNAL
TRISE
PWIN
PERIN
TFALL
2.4V VIH 2.4V
1.5V
1.5V
0.6V
0.6V
VIL
TDAR
TDAF
1.5V
VOH
1.5V
Timing Diagram For Testing
VOL
Doc #97001
3/25/04
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
5
5 Page | ||
| Páginas | Total 5 Páginas | |
| PDF Descargar | [ Datasheet PDU13F.PDF ] | |
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