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PDF PDU138 Data sheet ( Hoja de datos )
| Número de pieza | PDU138 | |
| Descripción | 3-BIT PROGRAMMABLE DELAY LINE | |
| Fabricantes | Data Delay Devices | |
| Logotipo |  |
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3-BIT PROGRAMMABLE
DELAY LINE
(SERIES PDU138)
FEATURES
• Digitally programmable in 8 delay steps
• Monotonic delay-versus-address variation
• Precise and stable delays
• Input & outputs fully TTL interfaced & buffered
• 10 T2L fan-out capability
• Fits standard 16-pin DIP socket
• Auto-insertable
PDU138
data
delay
3
®
devices, inc.
PACKAGES
N/C 1 16 VCC
N/C 2 15 N/C
N/C 3 14 N/C
IN 4 13 N/C
OUT 5 12 N/C
N/C 6 11 A0
EN/ 7 10 A1
GND 8 9 A2
PDU138-xx DIP
PDU138-xxM Military DIP
FUNCTIONAL DESCRIPTION
PIN DESCRIPTIONS
The PDU138-series device is a 3-bit digitally programmable delay line.
The delay, TDA, from the input pin (IN) to the output pin (OUT) depends on
the address code (A2-A0) according to the following formula:
IN
OUT
A2
TDA = TD0 + TINC * A
A1
A0
where A is the address code, TINC is the incremental delay of the device,
and TD0 is the inherent delay of the device. The incremental delay is
specified by the dash number of the device and can range from 0.5ns
EN/
VCC
GND
through 50ns, inclusively. The enable pin (EN/) is held LOW during normal
operation. When this signal is brought HIGH, OUT is forced into the LOW
state. The address is not latched and must remain asserted during normal operation.
Delay Line Input
Non-inverted Output
Address Bit 2
Address Bit 1
Address Bit 0
Output Enable
+5 Volts
Ground
SERIES SPECIFICATIONS
• Total programmed delay tolerance: 5% or 1ns,
whichever is greater
• Inherent delay (TD0): 7ns typical (OUT)
• Setup time and propagation delay:
Address to input setup (TAIS): 12ns typ.
Disable to output delay (TDISO): 12ns typ.
• Operating temperature: 0° to 70° C
• Temperature coefficient: 100PPM/°C (excludes TD0)
• Supply voltage VCC: 5VDC ± 5%
• Supply current: ICCH = 45ma
ICCL = 20ma
• Minimum pulse width: 20% of total delay
DASH NUMBER SPECIFICATIONS
Part
Number
PDU138-.5
PDU138-1
PDU138-2
PDU138-5
PDU138-10
PDU138-12
PDU138-15
PDU138-20
PDU138-40
PDU138-50
Incremental Delay
Per Step (ns)
.5 ± .3
1 ± .4
2 ± .4
5 ± .6
10 ± 1.0
12 ± 1.2
15 ± 1.3
20 ± 1.5
40 ± 2.0
50 ± 2.5
Total Delay
Change (ns)
3.5 ± 1.0
7 ± 1.0
14 ± 1.0
35 ± 1.8
70 ± 3.5
84 ± 4.2
105 ± 5.3
140 ± 7.0
280 ± 14.0
350 ± 17.5
NOTE: Any dash number between .5 and 50 not
shown is also available.
©2002 Data Delay Devices
Doc #02004
5/6/02
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
1 page  
PDU138
DELAY LINE AUTOMATED TESTING
TEST CONDITIONS
INPUT:
Ambient Temperature: 25oC ± 3oC
Supply Voltage (Vcc): 5.0V ± 0.1V
Input Pulse:
High = 3.0V ± 0.1V
Low = 0.0V ± 0.1V
Source Impedance: 50Ω Max.
Rise/Fall Time:
3.0 ns Max. (measured
between 0.6V and 2.4V )
Pulse Width:
PWIN = 1.5 x Total Delay
Period:
PERIN = 4.5 x Total Delay
OUTPUT:
Load:
Cload:
Threshold:
1 FAST-TTL Gate
5pf ± 10%
1.5V (Rising & Falling)
NOTE: The above conditions are for test only and do not in any way restrict the operation of the device.
COMPUTER
SYSTEM
PRINTER
PULSE
GENERATOR
OUT
TRIG
IN DEVICE UNDER OUT
TEST (DUT)
REF
IN
TRIG
TIME INTERVAL
COUNTER
Test Setup
INPUT
SIGNAL
OUTPUT
SIGNAL
TRISE
PWIN
PERIN
TFALL
2.4V VIH 2.4V
1.5V
1.5V
0.6V
0.6V
VIL
TDAR
TDAF
1.5V
VOH
1.5V
Timing Diagram For Testing
VOL
Doc #02004
5/6/02
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
5
5 Page | ||
| Páginas | Total 5 Páginas | |
| PDF Descargar | [ Datasheet PDU138.PDF ] | |
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