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PDF ICS9148-25 Data sheet ( Hoja de datos )
| Número de pieza | ICS9148-25 | |
| Descripción | Pentium/Pro System and Cyrix Clock Chip | |
| Fabricantes | ICST | |
| Logotipo |  |
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Integrated
Circuit
Systems, Inc.
ICS9148-25
Pentium/ProTM System and Cyrix™ Clock Chip
General Description
The ICS9148-25 is a Clock Synthesizer chip for Pentium and
PentiumPro plus Cyrix CPU based Desktop/Notebook systems
that will provide all necessary clock timing.
Features include four CPU, seven PCI and eight SDRAM
clocks. Two reference outputs are available equal to the crystal
frequency, plus the IOAPIC output powered by VDDL.
Additionally, the device meets the Pentium power-up
stabilization, which requires that CPU and PCI clocks be stable
within 2ms after power-up.
High drive PCICLK and SDRAM outputs typically provide
greater than 1 V/ns slew rate into 30pF loads. CPUCLK outputs
typically provide better than 1V/ns slew rate into 20pF loads
while maintaining 50 ±5% duty cycle. The REF clock outputs
typically provide better than 0.5V/ns slew rates.
The ICS9148-25 accepts a 14.318MHz reference crystal or
clock as its input and runs on a 3.3V supply.
Sperad Spectrum is modulated in center-spread mode on CPU/
SDRAM/PCI clocks. Modulation amount is selectable at
power-up (latched inputs) for ±0.5, ±1.0, ±2.0 or No spreading.
Features
• Generates system clocks for CPU, IOAPIC, SDRAM,
PCI, plus 14.318 MHz ), USB, Plus Super I/O
• Spread spectrum for CPU/SDRAM/PCI clocks default
• Supports single or dual processor systems
• Modulation of Spread Spectrum selectable as ±0.5, ±1.0,
±2.0 or none
• Supports Intel 60, 66.8MHz, Cyrix 55, 75MHz plus 83.3
and 68MHz (Turbo of 66.6) speeds.
• Synchronous clocks skew matched to 250ps window on
CPU, SDRAM and 500ps window on PCI clocks
• CPU clocks to PCI clocks skew 1-4ns (CPU early)
• MODE input pin selects optional power management
input control pins
• Two fixed outputs, 48MHz and 24 MHz
• Separate 2.5V and 3.3V supply pins
- 2.5V or 3.3V output: CPU, IOAPIC (Strength
selectable)
- 3.3V outputs: SDRAM, PCI, REF, 48/24 MHz
• No power supply sequence requirements
• 48 pin 300 mil SSOP
Pin Configuration
Block Diagram
Pentium is a trademark on Intel Corporation.
9148-25 Rev B 5/20/99
48-Pin SSOP
Power Groups
VDD = Supply for PLL core.
VDD1 = REF (0:2), X1, X2
VDD2 = PCICLK_F, PCICLK (0:5)
VDD3 = SDRAM (0:5), SDRAM6/CPU_STOP#,
SDRAM7/PCI_STOP#
VDD4 = 48MHz, 24MHz
VDDL1 = IOAPIC
VDDL2 = CPUCLK (0:3)
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
1 page  
ICS9148-25
Technical Pin Function Descriptions
CPU3.3_2.5#
This Input pin controls the CPU and IOAPIC output buffer
strength for skew matching CPU and SDRAM outputs to
compensate for the external VDDL supply condition. It is
important to use this function when selecting power supply
requirements for VDDL1,2. Alogic “0” (ground) will indicate
2.5V operation and a logic “1” will indicate 3.3V operation.
This pin has an internal pull-up to VDD. This pin is a latched
input.
PD#
This is an asynchronous active Low Input pin used to Power
Down the device into a Low Power state by not removing the
power supply. The internal Clocks are disabled and the VCO
and Crystal are stopped. Powered Down will also place all the
Outputs in a low state at the end of their current cycle. The
latency of Power Down will not be greater than 3ms. This pin
is a Full-time input with a pull-up to VDD.
CPU_STOP#
This is a active Low Input pin used to stop the CPUCLK
clocks in an active low state. All other clocks will continue to
run while this function is enabled. The CPUCLK’s will have a
turn OFF latency and a turn ON latency of 2 or 3 CPU clocks.
This pin is a Full-time input with a pull-up to VDD.
PCI_STOP#
This is a synchronous active Low Input pin used to stop the
PCICLK (0:5) clocks in a low state. It will not effect PCICLK_F
or any other outputs. There is only one full PCI clock output
for Turn OFF or Turn ON latency. This pin is a Full-time input
with a pull-up to VDD.
SSM (0:1)
These pins define the input condition for the Spread Spectrum
amount of modulation. See Spread Spectrum functionality
table. Note that spreading is only done on the CPU/SDRAM/
PCI clocks no modulation is done on the REF, IOAPIC or
PLL2 (24, 48MHz) outputs.
These latched input pins are defined at power-on for logic Hi
or logic Low condition by external pull-up or pull-down
resistors, or the internal pull-up resistor to VDD. See shared
pin operation of Input/output pins on next page.
5
5 Page 
ICS9148-25
Electrical Characteristics-REF1, 48MHz, & 24MHz
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 - 45 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
Output Impedance
RDSP7 VO = VDD*(0.5)
Output Impedance
RDSN7 VO = VDD*(0.5)
Output High Voltage
VOH7 IOH = -30 mA
Output Low Voltage
VOL7 IOL = 23 mA
Output High Current
IOH7
VOH = 2.0 V
Output Low Current
Rise Time
Fall Time
Duty Cycle
Jitter
IOL7
Tr71
Tf71
Dt71
tjcyc-cyc71
Tj1s71
Tj
1
abs7
VOL = 0.8 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
VT = 1.5 V
VT = 1.5 V
VT = 1.5 V
1Guarenteed by design, not 100% tested in production.
MIN
10
10
2.6
40
TYP MAX UNITS
24 Ω
24 Ω
2.75 V
0.3 0.4 V
-62 -40 mA
50 mA
1.4 2 ns
1.4 2 ns
45 54 55 %
1400 ps
210 400 ps
-1000 450 1000 ps
Electrical Characteristics - REF0
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 - 45 pF (unless otherwise stated)
PARAMETER SYMBOL
CONDITIONS
Output Impedance
RDSP7 VO = VDD*(0.5)
Output Impedance
RDSN7 VO = VDD*(0.5)
Output High Voltage VOH7 IOH = -30 mA
Output Low Voltage
VOL7 IOL = 23 mA
Output High Current
IOH7 VOH = 2.0 V
Output Low Current
IOL7 VOL = 0.8 V
Rise Time
Tr71 VOL = 0.4 V, VOH = 2.4 V
Fall Time
Tf71 VOH = 2.4 V, VOL = 0.4 V
Duty Cycle
Dt71 VT = 1.5 V
Jitter
tjcyc-cyc71
Tj1s71
Tjabs71
VT = 1.5 V
VT = 1.5 V
VT = 1.5 V
1Guarenteed by design, not 100% tested in production.
MIN
10
10
2.6
41
40
-1000
TYP
2.75
0.3
-62
50
1.8
1.8
54
1400
350
900
MAX UNITS
24 Ω
24 Ω
V
0.4 V
-54 mA
mA
2.2 ns
2.2 ns
60 %
ps
400 ps
1000 ps
11
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet ICS9148-25.PDF ] | |
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