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PDF AD7764 Data sheet ( Hoja de datos )
| Número de pieza | AD7764 | |
| Descripción | 109 dB Sigma-Delta ADC | |
| Fabricantes | Analog Devices | |
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24-Bit, 312 kSPS, 109 dB Sigma-Delta ADC
with On-Chip Buffers and Serial Interface
AD7764
FEATURES
High performance 24-bit ∑-∆ ADC
115 dB dynamic range at 78 kHz output data rate
109 dB dynamic range at 312 kHz output data rate
312 kHz maximum fully filtered output word rate
Pin-selectable oversampling rate (64×, 128×, and 256×)
Low power mode
Flexible SPI
Fully differential modulator input
On-chip differential amplifier for signal buffering
On-chip reference buffer
Full band low-pass finite impulse response (FIR) filter
Overrange alert pin
Digital gain correction registers
Power-down mode
Synchronization of multiple devices via SYNC pin
Daisy chaining
APPLICATIONS
Data acquisition systems
Vibration analysis
Instrumentation
FUNCTIONAL BLOCK DIAGRAM
VOUTA– VOUTA+ VIN+ VIN–
MCLK GND
VINA+
VINA–
DIFF
VREF+
BUF
MULTIBIT
Σ-Δ
MODULATOR
RECONSTRUCTION
AVDD1
AVDD2
AVDD3
AVDD4
DVDD
OVERRANGE
REFGND
SYNC
RESET/PWRDWN
INTERFACE LOGIC AND
OFFSET AND GAIN
CORRECTION REGISTERS
DECIMATION
FIR FILTER ENGINE
AD7764
FSO SCO SDI SDO FSI
Figure 1.
DEC_RATE
RBIAS
Table 1. Related Devices
Part No. Description
AD7760 2.5 MSPS, 100 dB, parallel output on-chip buffers
AD7762 625 kSPS, 109 dB, parallel output on-chip buffers
AD7763 625 kSPS, 109 dB, serial output, on-chip buffers
AD7765 156 kSPS, 112 dB, serial output, on-chip buffers
AD7766 128/64/32 kSPS, 8.5 mW, 109 dB SNR
AD7767 128/64/32 kSPS, 8.5 mW, 109 dB SNR
GENERAL DESCRIPTION
The AD7764 is a high performance, 24-bit sigma-delta (Σ-Δ)
analog-to-digital converter (ADC). It combines wide input
bandwidth, high speed, and performance of 109 dB dynamic
range at a 312 kHz output data rate. With excellent dc
specifications, the converter is ideal for high speed data
acquisition of ac signals where dc data is also required.
Using the AD7764 eases the front-end antialias filtering
requirements, simplifying the design process significantly. The
AD7764 offers pin-selectable decimation rates of 64×, 128×,
and 256×. Other features include an integrated buffer to drive
the reference, as well as a fully differential amplifier to buffer
and level shift the input to the modulator.
An overrange alert pin indicates when an input signal has
exceeded the acceptable range. The addition of internal gain
and internal overrange registers makes the AD7764 a compact,
highly integrated data acquisition device requiring minimal
peripheral components.
The AD7764 also offers a low power mode, significantly
reducing power dissipation without reducing the output data
rate or available input bandwidth.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
The differential input is sampled at up to 40 MSPS by an analog
modulator. The modulator output is processed by a series of
low-pass filters. The external clock frequency applied to the
AD7764 determines the sample rate, filter corner frequencies,
and output word rate.
The AD7764 device boasts a full band on-board FIR filter. The
full stop-band attenuation of the filter is achieved at the Nyquist
frequency. This feature offers increased protection from signals
that lie above the Nyquist frequency being aliased back into the
input signal bandwidth.
The reference voltage supplied to the AD7764 determines the
input range. With a 4 V reference, the analog input range is
±3.2768 V differential, biased around a common mode of
2.048 V. This common-mode biasing can be achieved using
the on-chip differential amplifier, further reducing the external
signal conditioning requirements.
The AD7764 is available in a 28-lead TSSOP package and is
specified over the industrial temperature range of −40°C
to +85°C.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2007-2009 Analog Devices, Inc. All rights reserved.
1 page  
AD7764
Parameter
Decimate 64×
Normal Power Mode
Dynamic Range
Test Conditions/Comments
MCLK = 40 MHz, ODR = 312.5 kHz, fIN = 1 kHz sine wave
Modulator inputs shorted
Signal-to-Noise Ratio (SNR)2
Differential amplifier inputs shorted
Spurious-Free Dynamic Range (SFDR)
Total Harmonic Distortion (THD)
Intermodulation Distortion (IMD)
Low Power Mode
Dynamic Range
Nonharmonic
Input amplitude = −0.5 dB
Input amplitude = −6 dB
Input amplitude = −6 dB, fIN A = 100.3 kHz, fIN B = 97.3 kHz
Second-order terms
Third-order terms
Modulator inputs shorted
Signal-to-Noise Ratio (SNR)2
Differential amplifier inputs shorted
Input amplitude = −0.5 dB
Spurious-Free Dynamic Range (SFDR)
Total Harmonic Distortion (THD)
Nonharmonic
Input amplitude = −0.5 dB
Input amplitude = −6 dB
DC ACCURACY
Resolution
Integral Nonlinearity
Zero Error
Guaranteed monotonic to 24 bits
Normal power mode
Low power mode
Normal power mode
Including on-chip amplifier
Low power mode
Gain Error
Zero Error Drift
Gain Error Drift
DIGITAL FILTER CHARACTERISTICS
Pass-Band Ripple
Pass Band3
−3 dB Bandwidth3
Stop Band3
Stop-Band Attenuation
Group Delay
Decimate 64×
Decimate 128×
Decimate 256×
ANALOG INPUT
Differential Input Voltage
Input Capacitance
Including on-chip amplifier
−1 dB frequency
Beginning of stop band
Decimate 64× and decimate 128× modes
Decimate 256×
MCLK = 40 MHz
MCLK = 40 MHz
MCLK = 40 MHz
Modulator input pins: VIN+ − VIN−, VREF+ = 4.096 V
At on-chip differential amplifier inputs
At modulator inputs
Specification Unit
109
105
107.3
104
102.7
130
−105
−103
dB typ
dB min
dB typ
dB typ
dB min
dBFS typ
dB typ
dB typ
−118
−108
dB
dB
106
105
105.3
103
102
110
−105
−111
−100
dB typ
dB min
dB typ
dB min
dBFS typ
dB typ
dB typ
dB max
24
0.0036
0.0014
0.006
0.03
0.04
0.002
0.024
0.018
0.04
0.00006
0.00005
Bits
% typ
% typ
% typ
% max
% typ
% typ
% max
% typ
% typ
%FS/°C typ
%FS/°C typ
0.1
ODR × 0.4016
ODR × 0.4096
ODR × 0.5
−120
−115
dB typ
kHz
kHz
kHz
dB typ
dB typ
89 µs typ
177 µs typ
358 µs typ
±3.2768
5
29
V p-p
pF typ
pF typ
Rev. A | Page 4 of 32
5 Page 
AD7764
Pin No.
14
15
16
19
18
Mnemonic
FSI
SYNC
RESET/
PWRDWN
MCLK
DEC_RATE
Description
Frame Sync Input. The status of this pin is checked on the falling edge of SCO. If this pin is low, then the first
data bit is latched in on the next SCO falling edge. See the AD7764 Interface section for further details.
Synchronization Input. A falling edge on this pin resets the internal filter. This can be used to synchronize
multiple devices in a system. See the Synchronization section for further details.
Reset/Power-Down Pin. When a logic low is sensed on this pin, the part is powered down and all internal
circuitry is reset.
Master Clock Input. A low jitter digital clock must be applied to this pin. The output data rate depends on the
frequency of this clock. See the Clocking the AD7764 section for more details.
Decimation Rate. This pin selects one of the three decimation rate modes. When 2.5 V is applied to this pin,
a decimation rate of 64× is selected. A decimation rate of 128× is selected by leaving the pin floating. A
decimation rate of 256× is selected by setting the pin to ground.
Rev. A | Page 10 of 32
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD7764.PDF ] | |
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