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PDF IDT77252 Data sheet ( Hoja de datos )
| Número de pieza | IDT77252 | |
| Descripción | 155 Mbps ATM SAR Controller | |
| Fabricantes | IDT | |
| Logotipo |  |
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155 Mbps ATM SAR Controller
With ABR Support for PCI-based
Networking Applications
IDT77252
x Full-duplex Segmentation and Reassembly (SAR) at 155
Mbps "wire-speed" (310 Mbps aggregate speed)
x Operates with ATM Networks up to 155.52 Mbps
x Stand-alone Controller: Embedded Processor not required
x Performs ATM Layer Protocol Functions
x Supports AAL5, AAL3/4, AAL0 and Raw Cell Formats
x Supports Constant Bit Rate (CBR), Variable Bit Rate (VBR),
and Unassigned Bit Rate (UBR), and Available Bit Rate
(ABR) Service Classes
x Segments and Reassembles CS-PDUs into Host Memory
x Up to 16K Open Transmit Connections
x Up to 16K Simultaneous Receive Connections
x ABR, VBR, UBR Selectable per VC Time-out
x Automatic AAL5 Padding
x Four Buffer Pools for Independent or Chained Reassembly
x Supports Any Buffer Alignment Condition
x Free Buffer Queues Mapped Into PCI Memory Space
x Rx FIFO Size (Configurable to 1024 Kbytes)
x Configurable Transmit FIFO Depth for Reduced Latency
x Supports Big and Little Endian Data Transfers
x Null Cell Disable Option During Transmit
x NAND Test Mode
x RM Cell Handling
x UTOPIA Level 1 Interface to PHY
x Utility Bus Interface for PHY Management
x Serial EEPROM Interface
x EPROM Interface
x PCI 2.1 Compliant
x UNI 3.1, TM 4.0 Compliant
x Meets PCI Bus Power Management and Interface
Specification Revision 1.1
x Pin Compatible with IDT 77211 SAR
x Commercial and Industrial Temperature Ranges
x 208-Lead PQFP Package (28 x 28mm)
x Software Drivers:
– SARWIN 2 Demonstration Program
– NDIS Driver
– Vx Works (3rd party)
– Linux (3rd party)
The IDT77252 NICStAR™ is a member of IDT's family of products for
Asynchronous Transfer Mode (ATM) networks. The ABR SAR performs
both the ATM Adaptation Layer (AAL) Segmentation and Reassembly
(SAR) function and the ATM layer protocol functions.
A Network Interface Card (NIC) or internetworking product based on
the ABR SAR uses host memory, rather than local memory, to reas-
semble Convergence Sublayer Protocol Data Units (CS-PDUs) from
ATM cell payloads received from the network. When transmitting, as CS-
PDUs become ready, they are queued in host memory and segmented
PCI BUS
16K x 32 to 512K x 32
SRAM
EPROM
32 8
33MHZ
32
IDT77252
155Mbps
PCI ATM
ABR SAR
2001 Integrated Device Technology, Inc.
EEPROM
Rx UTOPIA Bus
Tx UTOPIA Bus
8
8
Utility Bus
8
80.0MHZ OSC.
PHY
155Mbps 2
2
1 of 17
4057 drw 01
March 26, 2001
DSC 4057/8
1 page  
IDT77252
53 VCC
54 GND
55 C/BE(0)
56 AD(7)
57 VCC
58 AD(6)
59 AD(5)
60 AD(4)
61 GND
62 SR_A17
63 AD(3)
64 AD(2)
65 AD(1)
66 AD(0)
67 GND
68 SR_A15
69 SR_WE
70 SR_A13
71 SR_A8
72 SR_A9
73 SR_A11
74 SR_OE
75 SR_A10
76 SR_CS
77 SR_A16
78 GND
79 SR_A14
80 VCC
81 SR_A12
82 SR_A7
83 SR_A6
84 SR_A5
85 SR_A4
86 SR_A3
87 SR_A2
88 SR_A1
89 SR_A0
90 SR_A18
91 GND
I
I
I/O
I/O
I
I/O
I/O
I/O
I
O
I/O
I/O
I/O
I/O
I
O
O
O
O
O
O
O
O
O
O
I
O
I
O
O
O
O
O
O
O
O
O
O
I
power
power
PCI
PCI
power
PCI
PCI
PCI
power
SRAM
PCI
PCI
PCI
PCI
power
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
power
SRAM
power
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
power
bus command
address/data line
address/data line
address/data line
address/data line
Address line
address/data line
address/data line
address/data line
address/data line
Address line
Write enable
Address line
Address line
Address line
Address line
Output Enable control
Address line
Chip Select
Address line
Address line
Address line
Address line
Address line
Address line
Address line
Address line
Address line
Address line
Address line
Address line
5 of 17
March 26, 2001
5 Page 
IDT77252
!
CLK_OUT
RST
CLK
GNT
REQ
AD[31]
AD[30]
AD[29]
AD[28]
AD[27]
AD[26]
AD[25]
AD[24]
C/BE[3]
IDSEL
AD[23]
AD[22]
AD[21]
AD[20]
AD[19]
AD[18]
AD[17]
AD[16]
C/BE[2]
Frame
IRDY
TRDY
DEVSEL
STOP
INITA
PERR
SERR
PAR
C/BE[1]
AD[15]
AD[14]
AD[13]
198
203
204
205
206
2
3
4
5
6
7
10
11
12
13
14
15
18
20
21
22
23
24
27
29
30
31
32
33
36
38
39
40
41
42
45
46
! !
AD[12]
47 SR_I/O[06]
AD[11]
48 SR_I/O[07]
AD[10]
49 SR_I/O[08]
AD[9]
50 SR_I/O[09]
AD[8]
51 SR_I/O[10]
C/BE[0]
55 SR_I/O[11]
AD[7]
56 SR_I/O[12]
AD[6]
58 SR_I/O[13]
AD[5]
59 SR_I/O[14]
AD[4]
60 SR_I/O[15]
AD[3]
63 SR_I/O[16]
AD[2]
64 SR_I/O[17]
AD[1]
65 SR_I/O[18]
AD[0]
66 SR_I/O[19]
SR_WE
69 SR_I/O[20]
SR_A[13]
70 SR_I/O[21]
SR_A[8]
71 SR_I/O[22]
SR_A[9]
72 SR_I/O[23]
SR_A[11]
73 SR_I/O[24]
SR_OE
74 SR_I/O[25]
SR_A[10]
75 SR_I/O[26]
SR_CS
76 SR_I/O[27]
SR_A[12]
81 SR_I/O[28]
SR_A[7]
82 SR_I/O[29]
SR_A[6]
83 SR_I/O[30]
SR_A[5]
84 SR_I/O[31]
SR_A[4]
85 E_CE
SR_A[3]
86 EECS
SR_A[2]
87 EESCLK
SR_A[1]
88 EEDI
SR_A[0]
89 EEDO
SR_I/O[00]
92 SAR_CLK
SR_I/O[01]
93 UTL_AD[0]
SR_I/O[02]
94 UTL_AD[1]
SR_I/O[03]
95 UTL_AD[2]
SR_I/O[04]
96 UTL_AD[3]
SR_I/O[05]
97 UTL_AD[4]
Table 2 NAND Tree Pin Order
99
100
101
102
103
106
107
108
109
110
111
113
114
115
116
117
118
120
122
123
124
125
126
128
129
130
131
133
134
135
136
138
140
141
142
144
146
!
UTL_AD[5]
UTL_AD[6]
UTL_AD[7]
UTL_WR
UTL_RD
UTL_ALE
PHY_RST
PHY_INT
UTL_CS[0]
UTL_CS[1]
TxData[0]
TxData[1]
TxData[2]
TxData[3]
TxData[4]
TxData[5]
TxData[6]
TxData[7]
TxSOC
TxEnb
TxCLAV
TxCLK
RxData[0]
RxData[1]
RxData[2]
RxData[3]
RxData[4]
RxData[5]
RxData[6]
RxData[7]
RxSOC
RxEnb
RxCLAV
RxCLK
PHY_CLK
TxParity
147
148
149
151
152
153
154
155
158
159
160
161
162
163
165
166
168
169
171
172
173
174
176
177
178
179
181
182
183
184
185
186
187
189
190
191
11 of 17
March 26, 2001
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet IDT77252.PDF ] | |
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