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PDF IDT72T51546 Data sheet ( Hoja de datos )
| Número de pieza | IDT72T51546 | |
| Descripción | (IDT72T51546 / IDT72T51556) 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES | |
| Fabricantes | IDT | |
| Logotipo |  |
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ADVANCE INFORMATION
2.5V MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION
1,179,648 bits and 2,359,296 bits
IDT72T51546
IDT72T51556
FEATURES:
• Choose from among the following memory density options:
IDT72T51546 Total Available Memory = 1,179,648 bits
IDT72T51556 Total Available Memory = 2,359,296 bits
• Configurable from 1 to 32 Queues
• Queues may be configured at master reset from the pool of
Total Available Memory in blocks of 256 x 36
• Independent Read and Write access per queue
• User programmable via serial port
• User selectable I/O: 2.5V LVTTL, 1.5V HSTL, 1.8V eHSTL
• Default multi-queue device configurations
– IDT72T51546 : 1,024 x 36 x 32Q
– IDT72T51556 : 2,048 x 36 x 32Q
• 100% Bus Utilization, Read and Write on every clock cycle
• 200 MHz High speed operation (5ns cycle time)
• 3.6ns access time
• Echo Read Enable & Echo Read Clock Outputs
• Individual, Active queue flags (OV, FF, PAE, PAF, PR)
• 8 bit parallel flag status on both read and write ports
• Shows PAE and PAF status of 8 Queues
FUNCTIONAL BLOCK DIAGRAM
• Direct or polled operation of flag status bus
• Global Bus Matching - (All Queues have same Input Bus Width
and Output Bus Width)
• User Selectable Bus Matching Options:
– x36in to x36out
– x18in to x36out
– x9in to x36out
– x36in to x18out
– x36in to x9out
• FWFT mode of operation on read port
• Packet mode operation
• Partial Reset, clears data in single Queue
• Expansion of up to 8 multi-queue devices in parallel is available
• Power Down Input provides additional power savings in HSTL
and eHSTL modes.
• JTAG Functionality (Boundary Scan)
• Available in a 256-pin PBGA, 1mm pitch, 17mm x 17mm
• HIGH Performance submicron CMOS technology
• Industrial temperature range (-40°C to +85°C) is available
MULTI-QUEUE FLOW-CONTROL DEVICE
WADEN
FSTR
WRADD
8
WEN
WCLK
Din
x36
DATA IN
FF
PAF
PAFn
8
Q0
Q1
Q2
Q31
RADEN
ESTR
RDADD
8 REN
RCLK
EREN
ERCLK
OE
Qout
x36
DATA OUT
OV
PR
PAE
PAEn
8 PRn
5998 drw01
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
NOVEMBER 2003
DSC-5998/3
1 page  
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
DETAILED DESCRIPTION
MULTI-QUEUE STRUCTURE
The IDT multi-queue flow-control device has a single data input port and
single data output port with up to 32 FIFO queues in parallel buffering between
the two ports. The user can setup between 1 and 32 Queues within the device.
These queues can be configured to utilize the total available memory, providing
the user with full flexibility and ability to configure the queues to be various depths,
independent of one another.
MEMORY ORGANIZATION/ ALLOCATION
The memory is organized into what is known as “blocks”, each block being
256 x36 bits. When the user is configuring the number of queues and individual
queue sizes the user must allocate the memory to respective queues, in units
of blocks, that is, a single queue can be made up from 0 to m blocks, where m
is the total number of blocks available within a device. Also the total size of any
given queue must be in increments of 256 x36. For the IDT72T51546 and
IDT72T51556 the Total Available Memory is 128 and 256 blocks respectively
(a block being 256 x36). Queues can be built from these blocks to make any
size queue desired and any number of queues desired.
BUS WIDTHS
The input port is common to all queues within the device, as is the output port.
The device provides the user with Bus Matching options such that the input port
and output port can be either x9, x18 or x36 bits wide provided that at least one
of the ports is x36 bits wide, the read and write port widths being set
independently of one another. Because the ports are common to all queues the
width of the queues is not individually set, so that the input width of all queues
are equal and the output width of all queues are equal.
WRITING TO & READING FROM THE MULTI-QUEUE
Data being written into the device via the input port is directed to a discrete
queue via the write queue select address inputs. Conversely, data being read
from the device read port is read from a queue selected via the read queue select
address inputs. Data can be simultaneously written into and read from the same
queue or different queues. Once a queue is selected for data writes or reads,
the writing and reading operation is performed in the same manner as a
conventional IDT synchronous FIFO, utilizing clocks and enables, there is a
single clock and enable per port. When a specific queue is addressed on the
write port, data placed on the data inputs is written to that queue sequentially
based on the rising edge of a write clock provided setup and hold times are met.
Conversely, data is read on to the output port after an access time from a rising
edge on a read clock.
The operation of the write port is comparable to the function of a conventional
FIFO operating in standard IDT mode. Write operations can be performed on
the write port provided that the queue currently selected is not full, a full flag output
provides status of the selected queue. The operation of the read port is
comparable to the function of a conventional FIFO operating in FWFT mode.
When a queue is selected on the output port, the next word in that queue will
automatically fall through to the output register. All subsequent words from that
queue require an enabled read cycle. Data cannot be read from a selected
queueifthatqueueisempty,thereadportprovidesanOutputValidflagindicating
when data read out is valid. If the user switches to a queue that is empty, the
last word from the previous queue will remain on the output register.
As mentioned, the write port has a full flag, providing full status of the selected
queue. Along with the full flag a dedicated almost full flag is provided, this almost
full flag is similar to the almost full flag of a conventional IDT FIFO. The device
provides a user programmable almost full flag for all 32 queues and when a
respective queue is selected on the write port, the almost full flag provides status
for that queue. Conversely, the read port has an output valid flag, providing
status of the data being read from the queue selected on the read port. As well
as the output valid flag the device provides a dedicated almost empty flag. This
almost empty flag is similar to the almost empty flag of a conventional IDT FIFO.
The device provides a user programmable almost empty flag for all 32 queues
and when a respective queue is selected on the read port, the almost empty flag
provides status for that queue.
PROGRAMMABLE FLAG BUSSES
Inadditiontothesededicatedflags,full&almostfullonthewriteportandoutput
valid & almost empty on the read port, there are two flag status busses. An almost
full flag status bus is provided, this bus is 8 bits wide. Also, an almost empty flag
status bus is provided, again this bus is 8 bits wide. The purpose of these flag
busses is to provide the user with a means by which to monitor the data levels
within queues that may not be selected on the write or read port. As mentioned,
the device provides almost full and almost empty registers (programmable by
the user) for each of the 32 queues in the device.
In the IDT72T51546/72T51556 multi-queue flow-control devices the user
has the option of utilizing anywhere between 1 and 32 queues, therefore the
8 bit flag status busses are multiplexed between the 32 queues, a flag bus can
only provide status for 8 of the 32 queues at any moment, this is referred to as
a “Quadrant”, such that when the bus is providing status of queues 1 through
8, this is quadrant 1, when it is queues 9 through 16, this is quadrant 2 and so
on up to quadrant 4. If less than 32 queues are setup in the device, there are
still 4 quadrants, such that in “Polled” mode of operation the flag bus will still cycle
through 4 quadrants. If for example only 22 queues are setup, quadrants 1 and
2 will reflect status of queues 1 through 8 and 9 through 16 respectively.
Quadrant 3 will reflect the status of queues 17 through 22 on the least significant
6 bits, the most significant 2 bits of the flag bus are don’t care and the 4th quadrant
outputs will be don’t care also.
The flag busses are available in two user selectable modes of operation,
“Polled” or “Direct”. When operating in polled mode a flag bus provides status
of each quadrant sequentially, that is, on each rising edge of a clock the flag bus
is updated to show the status of each quadrant in order. The rising edge of the
write clock will update the almost full bus and a rising edge on the read clock will
update the almost empty bus. The mode of operation is always the same for both
the almost full and almost empty flag busses. When operating in direct mode, the
quadrant on the flag bus is selected by the user. So the user can actually address
the quadrant to be placed on the flag status busses, these flag busses operate
independently of one another. Addressing of the almost full flag bus is done via
the write port and addressing of the almost empty flag bus is done via the read
port.
PACKET READY
The multi-queue flow-control device also offers a “Packet Mode” operation.
Packet Mode is user selectable and requires the device to be configured with
both write and read ports as 36 bits wide. In packet mode, users can define the
length of packets or frame by using the two most significant bits of the 36-bit word.
Bit 34 is used to mark the Start of Packet (SOP) and bit 35 is used to mark the
End of Packet (EOP) as shown in Table 5). When writing data into a given queue
, the first word being written is marked, by the user setting bit 34 as the “Start
ofPacket”(SOP)andthelastwordwrittenismarkedasthe“EndofPacket”(EOP)
with all words written between the Start of Packet (SOP) marker (bit 34) and the
End of packet (EOP) packet marker (bit 35) constituting the entire packet. A
packet can be any length the user desires, up to the total available memory in
the multi-queue device. The device monitors the SOP (bit 34) and looks for the
word that contains the EOP (bit 35). The read port is supplied with an additional
5
5 Page 
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
PIN DESCRIPTIONS (CONTINUED)
Symbol &
Pin No.
REN
(T11)
SCLK
(N3)
SENI
(M2)
SENO
(M1)
SI
(L1)
SO
(M3)
TCK(2)
(A8)
TDI(2)
(B9)
TDO(2)
(A9)
TMS(2)
(B8)
TRST(2)
(C7)
Name
I/O TYPE
Description
Read Enable
HSTL-LVTTL The REN input enables read operations from a selected Queue based on a rising edge of RCLK.
INPUT A queue to be read from can be selected via RCLK, RADEN and the RDADD address bus regardless
of the state of REN. Data from a newly selected queue will be available on the Qout output bus on the second
RCLK cycle after queue selection regardless of REN due to the FWFT operation. A read enable is not
required to cycle the PAEn/PRn bus (in polled mode) or to select the PAEn quadrant , (in direct mode).
Serial Clock
HSTL-LVTTL
INPUT
If serial programming of the multi-queue device has been selected during master reset, the SCLK input
clocks the serial data through the multi-queue device. Data setup on the SI input is loaded into the device
ontherisingedgeofSCLKprovidedthat SENIisenabled,LOW.Whenexpansionofdevicesisperformed
the SCLK of all devices should be connected to the same source.
Serial Input
Enable
HSTL-LVTTL During serial programming of a multi-queue device, data loaded onto the SI input will be clocked into the
INPUT part (via a rising edge of SCLK), provided the SENI input of that device is LOW. If multiple devices are
cascaded,the SENIinputshouldbeconnectedtotheSENO outputofthepreviousdevice.Sowhenserial
loading of a given device is complete, its SENO output goes LOW, allowing the next device in the chain
to be programmed (SENOwill follow SENI of a given device once that device is programmed). TheSENI
input of the master device (or single device), should be controlled by the user.
Serial Output
Enable
HSTL-LVTTL This output is used to indicate that serial programming or default programming of the multi-queue device
OUTPUT has been completed. SENOfollowsSENI once programming of a device is complete. Therefore,SENO
will go LOW after programming provided SENI is LOW, once SENI is taken HIGH again, SENOwill also
go HIGH. When the SENOoutput goes LOW, the device is ready to begin normal read/write operations.
If multiple devices are cascaded and serial programming of the devices will be used, the SENO output
should be connected to the SENI input of the next device in the chain. When serial programming of the
first device is complete, SENO will go LOW, thereby taking the SENI input of the next device LOW and
so on throughout the chain. When a given device in the chain is fully programmed the SENO output
essentially follows the SENI input. The user should monitor the SENO output of the final device in the chain.
When this output goes LOW, serial loading of all devices has been completed.
Serial In
HSTL-LVTTL Duringserialprogrammingthispinisloadedwiththeserialdatathatwillconfigurethemulti-queuedevices.
INPUT Data present on SI will be loaded on a rising edge of SCLK provided that SENI is LOW. In expansion
mode the serial data input is loaded into the first device in a chain. When that device is loaded and its SENO
has gone LOW, the data present on SI will be directly output to the SO output. The SO pin of the first device
connects to the SI pin of the second and so on. The multi-queue device setup registers are shift registers.
Serial Out
HSTL-LVTTL This output is used in expansion mode and allows serial data to be passed through devices in the chain
OUTPUT to complete programming of all devices. The SI of a device connects to SO of the previous device in the
chain. The SO of the final device in a chain should not be connected.
JTAG Clock
LVTTL
INPUT
Clock input for JTAG function. One of four terminals required by IEEE Standard 1149.1-1990. Test
operations of the device are synchronous to TCK. Data from TMS and TDI are sampled on the rising edge
of TCK and outputs change on the falling edge of TCK. If the JTAG function is not used this signal needs
to be tied to GND.
JTAG Test Data LVTTL
Input INPUT
One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan operation,
test data serially loaded via the TDI on the rising edge of TCK to either the Instruction Register, ID Register
and Bypass Register. An internal pull-up resistor forces TDI HIGH if left unconnected.
JTAG Test Data LVTTL
Output
OUTPUT
One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan
operation, test data serially loaded output via the TDO on the falling edge of TCK from either the Instruction
Register, ID Register and Bypass Register. This output is high impedance except when shifting, while in
SHIFT-DR and SHIFT-IR controller states.
JTAG Mode
Select
LVTTL
INPUT
TMS is a serial input pin. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs the
device through its TAP controller states. An internal pull-up resistor forces TMS HIGH if left unconnected.
JTAG Reset
LVTTL
INPUT
TRST is an asynchronous reset pin for the JTAG controller. The JTAG TAP controller does not automatically
reset upon power-up, thus it must be reset by either this signal or by setting TMS= HIGH for five TCK cycles.
If the TAP controller is not properly reset then the outputs will always be in high-impedance. If the JTAG
function is used but the user does not want to use TRST, then TRST can be tied with MRS to ensure
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet IDT72T51546.PDF ] | |
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