|
|
PDF IDT23S08T Data sheet ( Hoja de datos )
| Número de pieza | IDT23S08T | |
| Descripción | 2.5V ZERO DELAY CLOCK MULTIPLIER | |
| Fabricantes | IDT | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de IDT23S08T (archivo pdf) en la parte inferior de esta página. Total 6 Páginas | ||
|
No Preview Available !
www.DataSheet4U.com
IDT23S08T
2.5V ZERO DELAY CLOCK MULTIPLIER
2.5V ZERO DELAY CLOCK
MULTIPLIER, SPREAD
SPECTRUM COMPATIBLE
COMMERCIALTEMPERATURERANGE
IDT23S08T
ADVANCE
INFORMATION
FEATURES:
• Phase-Lock Loop Clock Distribution for Applications ranging
from 10MHz to 133MHz operating frequency
• Distributes one clock input to two banks of four outputs
• Separate output enable for each output bank
• External feedback (FBK) pin is used to synchronize the outputs
to the clock input
• Output Skew <200 ps
• Low jitter <200 ps cycle-to-cycle
• 1/2x, 1x, 2x, 4x output options (see table):
– IDT23S08T-1 1x
– IDT23S08T-2 1x, 2x
– IDT23S08T-3 2x, 4x
– IDT23S08T-4 2x
– IDT23S08T-5 1/2x
• No external RC network required
• Operates at 2.5V VDD
• Spread spectrum compatible
• Available in SOIC package
DESCRIPTION:
The IDT23S08T is a high-speed phase-lock loop (PLL) clock multiplier. It
is designed to address high-speed clock distribution and multiplication applica-
tions. The zero delay is achieved by aligning the phase between the incoming
clock and the output clock, operable within the range of 10 to 133MHz.
The IDT23S08T has two banks of four outputs each that are controlled via
twoselectaddresses.Byproperselectionofinputaddresses, both bankscan
be put in tri-state mode. In test mode, the PLL is turned off, and the input clock
directly drives the outputs for system testing purposes. In the absence of an
input clock, the IDT23S08T enters power down. In this mode, the device will
draw less than 12µA, and the outputs are tri-stated.
The IDT23S08T is available in six unique configurations for both pre-
scaling and multiplication of the Input REF Clock. (See available options
table.)
The PLL is closed externally to provide more flexibility by allowing the user
to control the delay between the input clock and the outputs.
The IDT23S08T is characterized for Commercial operation.
FUNCTIONAL BLOCK DIAGRAM
(-3, -4)
16
FBK
2
1
REF
2
(-5)
PLL
2
CLKA1
3
CLKA2
14
CLKA3
15
CLKA4
S2 8
S1 9
Control
Logic
(-2, -3) 2
6
CLKB1
7
CLKB2
10
CLKB3
11
CLKB4
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
c 2003 Integrated Device Technology, Inc.
1
NOVEMBER 2003
DSC - 6510/4
1 page  
IDT23S08T
2.5V ZERO DELAY CLOCK MULTIPLIER
SWITCHING WAVEFORMS
VDD/2
t1
t2
VDD/2
Duty Cycle Timing
COMMERCIALTEMPERATURERANGE
VDD/2
Output
0.7V
t3
1.7V 1.7V
0.7V
t4
2.5V
0V
All Outputs Rise/Fall Time
VDD/2
Output
Output
t5
VDD/2
Output to Output Skew
VDD/2
Input
FBK
t6
VDD/2
Input to Output Propagation Delay
VDD/2
FBK, Device 1
FBK, Device 2
t7
VDD/2
Device to Device Skew
TEST CIRCUIT
0.1µF
0.1µF
VDD
OUTPUTS
CLKOUT
CLOAD
VDD
GND
GND
Test Circuit for all Parameters
5
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet IDT23S08T.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| IDT23S08 | 2.5V ZERO DELAY CLOCK MULTIPLIER | IDT |
| IDT23S08T | 2.5V ZERO DELAY CLOCK MULTIPLIER | IDT |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |