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PDF DP83222 Data sheet ( Hoja de datos )
| Número de pieza | DP83222 | |
| Descripción | CYCLONE Twisted Pair FDDI Stream Cipher Device | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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August 1994
DP83222
CYCLONETM Twisted Pair FDDI Stream Cipher Device
General Description
The DP83222 CYCLONE Stream Cipher Scrambler
Descrambler Device is an integrated circuit designed to in-
terface directly with the serial bit streams of a Twisted Pair
FDDI PMD The DP83222 is designed to be fully compatible
with the National Semiconductor FDDI Chip Sets including
the DP83223 TWISTERTM (Twisted Pair Transceiver) The
DP83222 requires a 125 MHz Transmit Clock and corre-
sponding Receive Clock for synchronous data scrambling
and descrambling The DP83222 is compliant with the ANSI
X3T9 5 TP-PMD draft standard and is required for the re-
duction of EMI emission over unshielded media The
DP83222 is specified to work in conjunction with existing
twisted pair transceiver signalling schemes such as MLT-3
or NRZI and enables high bandwidth transmission over
Twisted Pair copper media
Features
Y Enables 100 Mbps FDDI signalling over Category 5
Unshielded Twisted Pair (UTP) cable and Type 1
Shielded Twisted Pair (STP)
Y Reduces EMI emissions over Twisted Pair media
Y Compatible with ANSI X3T9 5 TP-PMD Standard
Y Requires a single a5V supply
Y Transparent mode of operation
Y Flexible NRZ and NRZI format options
Y Advanced BiCMOS process
Y Signal Detect and Clock Detect inputs provided for en-
hanced functionality
Y Suitable for Fiber Optic PMD replacement applications
Block Diagram
FIGURE 1 DP83222 Block Diagram
TL F 11885 – 1
CYCLONETM CDDTM CDLTM PLAYERTM PLAYERaTM and TWISTERTM are trademarks of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 11885
RRD-B30M105 Printed in U S A
1 page  
2 0 Pin Table
Signal
VCC
GND
ECLVCC
ECLGND
EXTVCC
RXDg
RXCg
TXDg
TXCg
SCOg
DSCOg
RXCOg
ENC0
ENC1
CD
SD
Pin No
7 16 28
1 4 11 15
21
22
23
32
56
18 17
13 14
19 20
27 26
24 25
9
8
10
12
TABLE I Pinout Summary
Description
VCC
GND
ECLVCC
ECLGND
External VCC
Received Data from PMD Receiver
125 MHz Clock from Receiver PLL
Transmit Data from PHY PMRD
125 MHz Clock from PHY
Scrambled Data to PMD Transmitter
Descrambled Data to PHY
Realigned 125 MHz Clock to PHY
Encode 0
Encode 1
Clock Detect Input from Receive PLL
Signal Detect Input from PMD Receiver
Type
Supply
Supply Return
Supply
Supply Return
Supply
Diff 100K ECL In
Diff 100K ECL In
Diff 100K ECL In
Diff 100K ECL In
Diff ECL Out
Diff ECL Out
Diff ECL Out
TTL Compatible CMOS In
TTL Compatible CMOS In
TTL Compatible CMOS In
Single-Ended ECL ln
3 0 Pin Definitions and Connection Diagrams
28-Pin PLCC
FIGURE 5 DP83222 Pinout
TL F 11885 – 4
VCC (7 16 28)
GND (1 4 11 15)
ECLVCC (21)
ECLGND (22)
EXTVCC (23)
RXDg (3 2)
RXCg (5 6)
Positive power supply for all internal
CMOS circuitry The Stream Cipher
Scrambler Descrambler operates from
a single a5V DC power supply
Return path for internal CMOS circuitry
power supply
Positive power supply for all internal
ECL circuitry This power supply is in-
tentionally separated from others to re-
duce coupled supply noise
Return path for all internal ECL circuit-
ry This Power supply return is inten-
tionally separated from others to re-
duce coupled supply noise
Positive power supply for emitter fol-
lower output circuitry
Differential 100K ECL data inputs
These inputs receive the ECL signals
generated by the National Semicon-
ductor DP83231 Clock Recovery De-
vice (CRDTM) or the DP83256 7VF-AP
Enhanced Physical Layer Devices
(PLAYER a TM )
Differential 100K ECL clock inputs
These inputs receive the 125 MHz
clock regenerated by the National
Semiconductor DP83231 Clock Re-
covery Device (CRD) the DP83257VF
or the DP83256VF-AP Enhanced
Physical Layer Devices (PLAYERa)
5
5 Page 
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet DP83222.PDF ] | |
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