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PDF VRS700 Data sheet ( Hoja de datos )

Número de pieza VRS700
Descripción Flash / MCU
Fabricantes Goal 
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VRS700
VERSA
Datasheet Rev 1.3
VERSA 700: 64kB FLASH, 4kB RAM
23MHz, 3V, 8-Bit MCU
Datasheet Rev 1.3
1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com
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VRS700 pdf
VRS700
VERSA
Datasheet Rev 1.3
Special Function Registers (SFR)
Addresses 80h to FFh of the SFR address space can be accessed in direct addressing mode only. The following table
lists the VRS700 Special Function Registers.
TABLE 4: SPECIAL FUNCTION REGISTERS (SFR)
SFR
SFR
Register Adrs
Bit 7
P0 80h -
SP 81h -
DPL 82h -
DPH 83h -
(Reserved) 84h
RCON
85h
-
DBANK
86h
BSE
PCON
87h SMOD
TCON 88h TF1
TMOD
89h GATE1
TL0 8Ah -
TL1 8Bh -
TH0 8Ch -
TH1 8Dh -
P1 90h -
WDTKEY 97h WDTKEY7
SCON 98h SM0
SBUF
99h
-
SPWME 9Bh SPWM7E
WDTC
9Fh WDTE
P2 A0h -
IE A8h EA
P3 B0h -
SPWMD0 B3h
-
SPWMD1 B4h
-
SPWMD2 B5h
-
SPWMD3 B6h
-
IP B8h -
SPWMD4 BBh
-
SPWMD5 BCh
-
SPWMD6 BDh
-
SPWMD7 BEh
-
SCONF
BFh
WDR
T2CON
C8h
TF2
T2MOD
C9h
-
RCAP2L CAh
-
RCAP2H CBh
-
TL2
CCh
-
TH2 CDh
PSW
D0h CY
SPWMC0 D3h
-
SPWMC1 D4h
-
SPWMC2 D5h
-
SPWMC3 D6h
-
P4 D8h -
SPWMC4 DBh
SPWMC5 DCh
SPWMC6 DDh
SPWMC7 DEh
ACC E0h -
B F0h -
Bit 6
-
-
-
-
-
-
-
TR1
C/T1
-
-
-
-
-
WDTKEY6
SM1
-
SPWM6E
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EXF2
-
-
-
-
AC
-
-
-
-
-
-
-
Bit 5
-
-
-
-
-
BS5
-
TF0
M1.1
-
-
-
-
-
WDTKEY5
SM2
-
SPWM5E
CLEAR
-
ET2
-
-
-
-
-
PT2
-
-
-
-
-
RCLK
-
-
-
-
F0
-
-
-
-
-
-
-
Bit 4
-
-
-
-
-
BS4
-
TR0
M0.1
-
-
-
-
-
WDTKEY4
REN
-
SPWM4E
-
-
ES
-
-
-
-
-
PS
-
-
-
-
-
TCLK
-
-
-
-
RS1
-
-
-
-
-
-
-
Bit 3
-
-
-
-
RAMS3
BS3
GF1
IE1
GATE0
-
-
-
-
-
WDTKEY3
TB8
-
SPWM3E
-
-
ET1
-
-
-
-
-
PT1
-
-
-
-
-
EXEN2
-
-
-
-
RS0
-
-
-
-
P4.3
-
-
Bit 2
-
-
-
-
RAMS2
BS2
GF0
IT1
C/T0
-
-
-
-
-
WDTKEY2
RB8
-
SPWM2E
PS2
-
EX1
-
-
-
-
-
PX1
-
-
-
-
TR2
-
-
-
-
OV
PBS0
PBS1
PBS2
PBS3
P4.2
PBS4
PBS5
PBS6
PBS7
-
-
Bit 1
-
-
-
-
RAMS1
BS1
PDOWN
IE0
M1.0
-
-
-
-
-
WDTKEY1
TI
-
SPWM1E
PS1
-
ET0
-
-
-
-
-
PT0
-
-
-
-
OME
C/T2
T2OE
-
-
-
-
PFS01
PFS11
PFS21
PFS31
P4.1
PFS41
PFS51
PFS61
PFS71
-
-
Bit 0
-
-
-
-
Reset
Value
RAMS0
BS0
IDLE
IT0
M0.0
-
-
-
-
-
WDTKEY0
RI
-
SPWM0E
PS0
-
EX0
-
-
-
-
-
PX0
-
-
-
-
ALEI
CP/RL2
DCEN
-
-
-
00000000b
0***0001b
00000000b
00000000b
00000000b
********b
00000000b
00000000b
0*0**000b
00000000b
00000000b
00000000b
00000000b
00000000b
00000000b
00000000b
00000000b
00000000b
00000000b
0****00b
00000000b
00000000b
P
PFS00
PFS10
PFS20
PFS30
P4.0
PFS40
PFS50
PFS60
PFS70
-
-
******00b
******00b
******00b
******00b
****1111b
******00b
******00b
******00b
******00b
1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com
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VRS700 arduino
VRS700
VERSA
Datasheet Rev 1.3
The transistor would be off and the pull-up will maintain
the output at a high level. Also, note that if an external
device with a logical low value is connected to the pin,
the current will flow out of the pin. In order to have a
real bi-directional output, the input should be in a high
impedance state. It is for this reason that we call ports
P1, P2, P3 and P4 “quasi bi-directional”.
Structure of Port 0
The internal structure of P0 is shown in Figure 6. The
auxiliary function of this port requires a particular logic.
As opposed to the other ports, P0 is truly bi-directional.
In other words, when used as an input, it is considered
to be in a floating logical state (high impedance state).
This arises from the absence of the internal pull-up
resistance. The pull-up resistance is actually replaced
by a transistor that is only used when the port is used
to access external memory/data bus (EA=0).
When used as an I/O port, P0 acts as an open drain
port and the use of an external pull-up resistor is likely
to be required for most applications.
FIGURE 6: PORT P0’S PARTICULAR STRUCTURE
Read Register
Address A0/A7
Co ntr ol
Internal Bus
W rite t o
Register
Q
D Flip-Flop
Q
Vcc
X1
IC Pin
Read Pin
When P0 is used as an external memory bus input (for
a MOVX instruction, for example), the outputs of the
register are automatically forced to 1.
Port P0 and P2 as Address and Data Bus
The output stage may receive data from two sources
(Figure 7):
The outputs of register P0 or the bus address
itself multiplexed with the data bus for P0.
The outputs of the P2 register or the high part
(A8/A15) of the bus address for the P2 port.
FIGURE 7: P2 PORT STRUCTURE
Read Register
Internal Bus
Write t o
Re gister
A ddress
Q
D Flip-Flop
Q
Co ntr ol
V cc
Pull-u p
Ne two rk
X1
I C Pin
Read P in
When the ports are used as an address or data bus,
the special function registers P0 and P2 are
disconnected from the output stage. The 8 bits of the
P0 register are forced to 1 and the content of the P2
register remains constant.
Auxiliary Port 1 Functions
The port 1 I/O pins are shared with the SPWM outputs,
Timer 2 EXT and T2 input as shown below:
Pin
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
Mnemonic
T2
SPWM0
T2EX
SPWM1
SPWM2
SPWM3
SPWM4
SPWM5
SPWM6
SPWM7
Function
Timer 2 counter input
SPWM0 output
Timer2 Auxiliary input
SPWM1 output
SPWM2 output
SPWM3 output
SPWM4output
SPWM5 output
SPWM6 output
SPWM7 output
1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com
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