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PDF VRS51X540 Data sheet ( Hoja de datos )
| Número de pieza | VRS51X540 | |
| Descripción | Versa 8051 MCU | |
| Fabricantes | Ramtron | |
| Logotipo |  |
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VRS51x540
Datasheet
Rev 1.2
Versa 8051 MCU with 4KB Flash
Overview
The VRS51x540 is a low cost 8-bit microcontroller
based on the standard 80C51 microcontroller family
architecture. It is pin compatible and is a drop-in
replacement for standard 8051 MCUs
Aimed at cost effective applications requiring small
amounts of program/data memory coupled with
streamlined peripheral support, the VRS51x540 includes
4KB of Flash memory, 128 bytes of RAM a UART, three
16-bit timers, a Watchdog timer and power down
features.
The VRS51x540 is available in 5 (VRS51C540) and 3.3
(VRS51L540) volt versions in PLCC-44, QFP-44 and
DIP-40 packages. The VRS51x540 devices operate
over the entire industrial temperature range. The Flash
memory can be programmed using programmers
available from Ramtron or other 3rd party commercial
programmers.
FIGURE 1: VRS51X540 FUNCTIONAL DIAGRAM
Feature Set
• 80C51/80C52 pin compatible
• 12 clock periods per machine cycle
• 4KB on-chip Flash memory
• 128 bytes on-chip data RAM
• 32 I/O lines: P0-P3 = 8-bit
• Full duplex serial port (UART)
• 3, 16-bit Timers/Counters
• Watchdog Timer
• 8-bit Unsigned Division / Multiply
• BCD arithmetic
• Direct and Indirect Addressing
• Two levels of interrupt priority and nested interrupts
• Power saving modes
• Code protection function
• Operates at a clock frequency of up to 40MHz
• Low EMI (inhibit ALE)
• Programming voltage: 12V
• Industrial Temperature range (-40°C to +85°C)
• 5V and 3V versions available (see ordering information.)
FIGURE 2: VRS51X540 PLCC AND QFP PINOUT DIAGRAMS
4KB
FLASH
128 Bytes of
RAM
8051
PROCESSOR
ADDRESS/
DATA BUS
PORT 0
PORT 1
UART
PORT 2
2 INTERRUPT
INPUTS
TIMER 0
TIMER 1
TIMER 2
RESET
POWER
CONTROL
WATCHDOG
TIMER
PORT 3
8
8
8
8
6 40
P1.5
7
1
39 P0.4/AD4
P1.6
P0.5/AD5
P1.7
P0.6/AD6
RESET
P0.7/AD7
RXD/P3.0
NC
TXD/P3.1
VRS51x540
PLCC -4 4
#EA
NC
ALE
#INT0/P3.2
#PSEN
#INT1/P3.3
P2.7/A15
T0/P3.4
P2.6/A14
T1/P3.5
17
18
29
28
P2.5/A13
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
VDD
NC
T2/P1.0
T2EX/P1.1
P1.2
P1.3
P1.4
32
3 3 32
42
VRS51x540
QFP-44
41
41
12
1
P2.4/A12
P2.3/A11
P2.2/A10
P2.1/A9
P2.0/A8
NC
VSS
XTAL1
XTAL2
#RD/P3.7
#WR/P3.6
Ramtron International Corporation ? http://www.ramtron.com
1850 Ramtron Drive Colorado Springs ? MCU customer service: 1-800-943-4625, 1-514-871-2447, ext. 208
Colorado, USA, 80921 ? 1-800-545-FRAM, 1-719-481-7000
page 1 of 40
1 page  
VRS51x540
Instruction Set
The following tables describe the instruction set of the
VRS51x540. The instructions are functional and binary
code compatible with industry standard 8051s.
TABLE 4: LEGEND FOR INSTRUCTION SET TABLE
Symbol
A
Rn
Direct
@Ri
Rel
Bit
#data
#data 16
addr 16
addr 11
Function
Accumulator
Register R0-R7
Internal register address
Internal register pointed to by R0 or R1 (except MOVX)
Two's complement offset byte
Direct bit address
8-bit constant
16-bit constant
16-bit destination address
11-bit destination address
TABLE 5: VRS51X540 INSTRUCTION SET
Mnemonic
Description
Arithmetic instructions
ADD A, Rn
Add register to A
ADD A, direct
Add direct byte to A
ADD A, @Ri
Add data memory to A
ADD A, #data
Add immediate to A
ADDC A, Rn
Add register to A with carry
ADDC A, direct
Add direct byte to A with carry
ADDC A, @Ri
Add data memory to A with carry
ADDC A, #data
Add immediate to A with carry
SUBB A, Rn
Subtract register from A with borrow
SUBB A, direct
Subtract direct byte from A with borrow
SUBB A, @Ri
Subtract data mem from A with borrow
SUBB A, #data
Subtract immediate from A with borrow
INC A
Increment A
INC Rn
Increment register
INC direct
Increment direct byte
INC @Ri
Increment data memory
DEC A
Decrement A
DEC Rn
Decrement register
DEC direct
Decrement direct byte
DEC @Ri
Decrement data memory
INC DPTR
Increment data pointer
MUL AB
Multiply A by B
DIV AB
Divide A by B
DA A
Decimal adjust A
Logical Instructions
ANL A, Rn
AND register to A
ANL A, direct
AND direct byte to A
ANL A, @Ri
AND data memory to A
ANL A, #data
AND immediate to A
ANL direct, A
AND A to direct byte
ANL direct, #data AND immediate data to direct byte
ORL A, Rn
OR register to A
ORL A, direct
OR direct byte to A
ORL A, @Ri
OR data memory to A
ORL A, #data
OR immediate to A
ORL direct, A
OR A to direct byte
ORL direct, #data OR immediate data to direct byte
XRL A, Rn
Exclusive-OR register to A
XRL A, direct
Exclusive-OR direct byte to A
XRL A, @Ri
Exclusive-OR data memory to A
XRL A, #data
Exclusive-OR immediate to A
XRL direct, A
Exclusive-OR A to direct byte
XRL direct, #data Exclusive-OR immediate to direct byte
CLR A
Clear A
CPL A
Compliment A
SWAP A
Swap nibbles of A
RL A
Rotate A left
RLC A
Rotate A left through carry
RR A
Rotate A right
RRC A
Rotate A right through carry
Size
(bytes)
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
1
1
1
2
1
1
1
1
1
1
2
1
2
2
3
1
2
1
2
2
3
1
2
1
2
2
3
1
1
1
1
1
1
1
Instr. Cycles
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
4
4
1
1
1
1
1
1
2
1
1
1
1
1
2
1
1
1
1
1
2
1
1
1
1
1
1
1
Mnemonic
Description
Size
(bytes)
Boolean Instruction
CLR C
Clear Carry bit
CLR bit
Clear bit
SETB C
Set Carry bit to 1
SETB bit
Set bit to 1
CPL C
Complement Carry bit
CPL bit
Complement bit
ANL C,bit
Logical AND between Carry and bit
ANL C,#bit
Logical AND between Carry and not bit
ORL C,bit
Logical ORL between Carry and bit
ORL C,#bit
Logical ORL between Carry and not bit
MOV C,bit
Copy bit value into Carry
MOV bit,C
Copy Carry value into Bit
Data Transfer Instructions
MOV A, Rn
Move register to A
MOV A, direct
Move direct byte to A
MOV A, @Ri
Move data memory to A
MOV A, #data
Move immediate to A
MOV Rn, A
Move A to register
MOV Rn, direct
Move direct byte to register
MOV Rn, #data
Move immediate to register
MOV direct, A
Move A to direct byte
MOV direct, Rn
Move register to direct byte
MOV direct, direct Move direct byte to direct byte
MOV direct, @Ri
Move data memory to direct byte
MOV direct, #data Move immediate to direct byte
MOV @Ri, A
Move A to data memory
MOV @Ri, direct
Move direct byte to data memory
MOV @Ri, #data
Move immediate to data memory
MOV DPTR, #data Move immediate to data pointer
MOVC A, @A+DPTR
Move code byte relative DPTR to A
MOVC A, @A+PC Move code byte relative PC to A
MOVX A, @Ri
Move external data (A8) to A
MOVX A, @DPTR Move external data (A16) to A
MOVX @Ri, A
Move A to external data (A8)
MOVX @DPTR, A Move A to external data (A16)
PUSH direct
Push direct byte onto stack
POP direct
Pop direct byte from stack
XCH A, Rn
Exchange A and register
XCH A, direct
Exchange A and direct byte
XCH A, @Ri
Exchange A and data memory
XCHD A, @Ri
Exchange A and data memory nibble
Branching Instructions
ACALL addr 11
Absolute call to subroutine
LCALL addr 16
Long call to subroutine
RET
Return from subroutine
RETI
Return from interrupt
AJMP addr 11
Absolute jump unconditional
LJMP addr 16
Long jump unconditional
SJMP rel
Short jump (relative address)
JC rel
Jump on carry = 1
JNC rel
Jump on carry = 0
JB bit, rel
Jump on direct bit = 1
JNB bit, rel
Jump on direct bit = 0
JBC bit, rel
Jump on direct bit = 1 and clear
JMP @A+DPTR
Jump indirect relative DPTR
JZ rel
Jump on accumulator = 0
JNZ rel
Jump on accumulator 1= 0
CJNE A, direct, rel
Compare A, direct JNE relative
CJNE A, #d, rel
Compare A, immediate JNE relative
CJNE Rn, #d, rel
Compare reg, immediate JNE relative
CJNE @Ri, #d, rel Compare ind, immediate JNE relative
DJNZ Rn, rel
Decrement register, JNZ relative
DJNZ direct, rel
Decrement direct byte, JNZ relative
Miscellaneous Instruction
NOP
No operation
Rn: Any of the register R0 to R7
@Ri: Indirect addressing using Register R0 or R1
#data: immediate Data provided with Instruction
#data16: Immediate data included with instruction
bit: address at the bit level
rel: relative address to Program counter from +127 to –128
Addr11: 11-bit address range
Addr16: 16-bit address range
#d: Immediate Data supplied with instruction
1
2
1
2
1
2
2
2
2
2
2
2
1
2
1
2
1
2
2
2
2
3
2
3
1
2
2
3
1
1
1
1
1
1
2
2
1
2
1
1
2
3
1
1
2
3
2
2
2
3
3
3
1
2
2
3
3
3
3
2
3
1
Instr. Cycles
1
1
1
1
1
1
2
2
2
2
1
2
1
1
1
1
1
2
1
1
2
2
2
2
1
2
1
2
2
2
2
2
2
2
2
2
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
______________________________________________________________________________________________
www.ramtron.com
page 5 of 40
5 Page 
VRS51x540
Auxiliary P3 Port Functions
The Port 3 I/O pins are shared with the UART
interface, INT0 and INT1 interrupts, Timer 0 and Timer
1 inputs and finally the #WR and #RD lines when
external memory access is performed.
FIGURE 10: P3 PORT STRUCTURE
Read Register
Auxiliary
Function: Output
Internal Bus
Write to
Register
Q
D Flip-Flop
Q
Vcc
X1
IC Pin
Read Pin
Auxiliary
Function: Input
The following table describes the auxiliary function of
the port 3 I/O pins.
TABLE 10: P3 AUXILIARY FUNCTION TABLE
Pin Mnemonic Function
P3.0 RXD
Serial Port:
Receive data in asynchronous
mode. Input and output data in
synchronous mode.
P3.1 TXD
Serial Port:
Transmit data in asynchronous
mode. Output clock value in
synchronous mode.
P3.2 INT0
External Interrupt 0
Timer 0 Control Input
P3.3 INT1
External Interrupt 1
Timer 1 Control Input
P3.4 T0
Timer 0 Counter Input
P3.5 T1
Timer 1 Counter Input
P3.6 WR
Write signal for external memory
P3.7 RD
Read signal for external memory
Software Particularities Concerning the Ports
Some instructions allow the user to read the logic state
of the output pin, while others allow the user to read
the content of the associated port register. These
instructions are called read-modify-write instructions. A
list of these instructions may be found in the table
below.
Upon execution of these instructions, the content of the
port register (at least 1-bit) is modified. The other read
instructions take the present state of the input into
account. For example, the instruction ANL P3, #01h
obtains the value in the P3 register; performs the
desired logic operation with the constant 01h; and re-
copies the result into the P3 register. When users want
to take the present state of the inputs into account,
they must first read these states and perform an AND
operation between the reading and the constant.
MOV A, P3; State of the inputs in the accumulator
ANL A, #01; AND operation between P3 and 01h
When the port is used as an output, the register
contains information on the state of the output pins.
Measuring the state of an output directly on the pin is
inaccurate because the electrical level depends mostly
on the type of charge that is applied to it. The functions
shown below take the value of the register rather than
that of the pin.
TABLE 11: LIST OF INSTRUCTIONS THAT READ AND MODIFY THE PORT USING REGISTER
VALUES
Instruction Function
ANL Logical AND ex: ANL P0, A
ORL
XRL
Logical OR ex: ORL P2, #01110000B
Exclusive OR ex: XRL P1, A
JBC Jump if the bit of the port is set to 0
CPL Complement one bit of the port
INC Increment the port register by 1
DEC
Decrement the port register by 1
DJNZ
Decrement by 1 and jump if the result
is not equal to 0
MOV P., C
CLR P.x
SETB P.x
Copy the held bit C to the port
Set the port bit to 0
Set the port bit to 1
______________________________________________________________________________________________
www.ramtron.com
page 11 of 40
11 Page | ||
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| PDF Descargar | [ Datasheet VRS51X540.PDF ] | |
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