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PDF VRS51C1100 Data sheet ( Hoja de datos )
| Número de pieza | VRS51C1100 | |
| Descripción | Versa 8051 MCU | |
| Fabricantes | Ramtron | |
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VRS51C1100
Datasheet
Rev 1.1
Versa 8051 MCU with 128KB of IAP/ISP Flash
Overview
The VRS51C1100 is based on the standard 8051
microcontroller architecture and is a pin compatible
drop-in replacement for the 8051.
The VRS51C1100 is aimed at a diversity of applications
that require a large amount of program/data memory
with non-volatile data storage and/or code/field based
firmware upgrade capability coupled with
comprehensive peripheral support. It features 64KB of
In-System/In-Application Programmable Flash memory,
64KB Data Flash memory, 1KB of RAM, 4 PWM
outputs, a UART, three 16-bit timers/counters, a
watchdog timer and power down features.
The VRS51C1000 is available with firmware that
enables In-System Programming (firmware based boot-
loader) of the Flash memory via the UART interface
(ISPVx version). General Flash memory programming
is supported by device programmers available from
Ramtron or other 3rd party commercial programmer
suppliers.
The VRS51C1100 is available in PLCC-44, QFP-44
and DIP-40 packages and functions over the industrial
temperature range.
FIGURE 1: VRS51C1100 FUNCTIONAL DIAGRAM
64KB
Data FLASH
64KB
Program
FLASH
1024 Bytes of
RAM
8051
PROCESSOR
ADDRESS/
DATA BUS
PORT 0
PORT 1
8
8
UART
PORT 2
8
2 INTERRUPT
INPUTS
TIMER 0
TIMER 1
TIMER 2
RESET
POWER
CONTROL
WATCHDOG
TIMER
PORT 3
PORT 4
PWM
8
4
4
Feature Set
• 80C51/80C52 pin compatible
• 64KB Program + 64KB Data Flash memory
• In-System / In-Application Flash Programming (ISP/IAP)
• Program voltage: 5V
• 1024 Bytes on chip data RAM
• Four 8-bit I/Os + one 4-bit I/O
• 4 PWM outputs on P1.3 to P1.7
• One Full Duplex UART serial port
• Three 16-bit Timers/Counters
• Watchdog Timer
• Bit operation instruction
• 8-bit Unsigned Multiply and Division instructions
• BCD arithmetic
• Direct and Indirect Addressing
• Two Levels of Interrupt Priority and Nested Interrupts
• Power saving modes
• Code protection function
• Low EMI (inhibit ALE)
• Operating Temperature Range -40ºC to +85ºC
FIGURE 2: VRS51C1100 QFP-44 AND PLCC-44 PIN OUT DIAGRAMS
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
VDD
P4.2
T2/P1.0
T2EX/P1.1
PWM0/P1.2
PWM1/P1.3
PWM2/P1.4
33
34
23
22
VRS51C1100
QFP-44
44
1
12
11
P2.4/A12
P2.3/A11
P2.2/A10
P2.1/A9
P2.0/A8
P4.0
VSS
XTAL1
XTAL2
#RD/P3.7
#WR/P3.6
PWM3/P1.5
P1.6
P1.7
RES
RXD/P3.0
P4.3
TXD/P3.1
#INT0/P3.2
#INT1/P3.3
T0/P3.4
T1/P3.5
6
7
17
18
40
39
VRS51C1000
PLCC-44
29
28
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
#EA
P4.1
ALE
#PSEN
P2.7/A15
P2.6/A14
P2.5/A13
Ramtron International Corporation ? http://www.ramtron.com
1850 Ramtron Drive Colorado Springs ? MCU customer service: 1-800-943-4625, 1-514-871-2447, ext. 208
Colorado, USA, 80921 ? 1-800-545-FRAM, 1-719-481-7000
page 1 of 50
1 page  
VRS51C1100
Special Function Registers (SFR)
Addresses 80h to FFh of the SFR address space can be accessed in direct addressing mode only. The following table
lists the VRS51C1100 special function registers.
TABLE 5: SPECIAL FUNCTION REGISTERS (SFR)
SFR
SFR
Register Adrs
Bit 7
P0 80h -
SP 81h -
DPL 82h -
DPH
83h -
MPAGE
85h
-
DBANK 86h BSE
PCON
87h SMOD
TCON
88h TF1
TMOD
89h GATE1
TL0 8Ah -
TL1 8Bh -
TH0 8Ch -
TH1 8Dh -
P1 90h -
WDTKEY 97h
-
SCON
98h SM0
SBUF 99h -
PWME
9Bh
-
WDTCTRL 9Fh
WDTE
P2 A0h -
PWMC
A3h
-
PWMD0
A4h PWMD0.4
PWMD1
A5h PWMD1.4
PWMD2
A6h PWMD2.4
PWMD3
A7h PWMD3.4
IE A8h EA
P3 B0h -
IP B8h -
SYSCON BFh
WDR
T2CON C8h TF2
RCAP2L
CAh
-
RCAP2H CBh
-
TL2
CCh
-
TH2 CDh
PSW
D0h CY
P4 D8h -
ACC
E0h -
B F0h -
IAPFADHI F4h
FA15
IAPFADLO F5h
FA7
IAPFDATA F6h
FD7
IAPFCTRL F7h IAPSTART
Bit 6
-
-
-
-
-
-
-
TR1
C/T1
-
-
-
-
-
-
SM1
-
-
-
-
-
PWMD0.3
PWMD1.3
PWMD2.3
PWMD3.3
-
-
-
-
EXF2
-
-
-
AC
-
-
-
FA14
FA6
FD6
Bit 5
-
-
-
-
-
-
-
TF0
M1.1
-
-
-
-
-
-
SM2
-
PWM3E
CLEAR
-
-
PWMD0.2
PWMD1.2
PWMD2.2
PWMD3.2
ET2
-
PT2
-
RCLK
-
-
-
F0
-
-
-
FA13
FA5
FD5
FZONE
Bit 4
-
-
-
-
-
-
-
TR0
M0.1
-
-
-
-
-
-
REN
-
PWM2E
-
-
-
PWMD0.1
PWMD1.1
PWMD2.1
PWMD3.1
ES
-
PS
-
TCLK
-
-
-
RS1
-
-
-
FA12
FA4
FD4
Bit 3
-
-
-
-
-
BS3
GF1
IE1
GATE0
-
-
-
-
-
-
TB8
-
PWM1E
-
-
-
PWMD0.0
PWMD1.0
PWMD2.0
PWMD3.0
ET1
-
PT1
DATAFE
EXEN2
-
-
-
RS0
P4.3
-
-
FA11
FA3
FD3
Bit 2
-
-
-
-
-
BS2
GF0
IT1
C/T0
-
-
-
-
-
-
RB8
-
PWM0E
PS2
-
-
NP0.2
NP1.2
NP2.2
NP3.2
EX1
-
PX1
IAPE
TR2
-
-
-
Bit 1
-
-
-
-
-
BS1
PDOWN
IE0
M1.0
-
-
-
-
-
-
TI
-
-
PS1
-
PDCK1
NP0.1
NP1.1
NP2.1
NP3.1
ET0
-
PT0
XRAME
C/T2
-
-
-
OV
P4.2
-
-
FA10
FA2
FD2
-
P4.1
-
-
FA9
FA1
FD1
IAPFCT1
Bit 0
-
-
-
-
-
BS0
IDLE
IT0
M0.0
-
-
-
-
-
-
RI
-
-
PS0
-
PDCK0
NP0.0
NP1.0
NP2.0
NP3.0
EX0
-
PX0
ALEI
CP/RL2
-
-
-
P
P4.0
-
-
FA8
FA0
FD0
IAPFCT0
Reset
Value
1111 1111b
0000 0111b
0000 0000b
0000 0000b
0000 0000b
0000 0001b
0000 0000b
0000 0010b
0000 0000b
0000 0000b
0000 0000b
0000 0000b
0000 0000b
1111 1111b
0000 0000b
0000 0000b
0111 1111b
0000 0000b
0000 0000b
1111 1111b
0000 0000b
0000 0000b
0000 0000b
0000 0000b
0000 0000b
0000 0000b
1111 1011b
0000 0000b
0000 1010b
0000 0000b
0000 0000b
0000 0000b
0000 0000b
0000 0000b
0000 0001b
****1111b
0000 0000b
0000 0000b
0000 0000b
0000 0000b
0000 0000b
______________________________________________________________________________________________
www.ramtron.com
page 5 of 50
5 Page 
VRS51C1100
Data Pointer
The VRS51C1100 has one 16-bit data pointer. The
DPTR is accessed via two SFR addresses: DPL
located at address 82h and DPH located at address
83h.
Stack Pointer
The stack pointer (SP) is a register located at address
81h of the SFR register area whose value corresponds
to the address of the last item that was put on the
processor stack. Each time new data is put on the SP,
the value of the stack pointer is incremented.
By default, the stack pointer value is 07h, but it is
possible to program the processor stack pointer to
point anywhere in the 00h to FFh range of RAM
memory. When a function call is performed or an
interrupt is serviced, the 16-bit return address (2 bytes)
is stored on the stack. Data can be placed manually on
the stack by using the PUSH and POP functions.
Data Memory
The VRS51C1100 has 1KB of on-chip RAM: 256 bytes
are configured like the internal memory structure of a
standard 8052, while the remaining 768 bytes can be
accessed using external memory addressing (MOVX).
The VRS51C1100 also includes a large block of 64KB
of data Flash that is mapped on the processor’s external
memory bus for read access.
FIGURE 6: VRS51C1100 DATA MEMORY STRUCTURE
FFFFh
IF DFLASHE = 1
Data Flash
Mapped as
External Memory
Use MOVX to Read
FFh
80h
7Fh
00h
Upper 128 bytes RAM
(Indirect addressing only)
Lower 128 bytes RAM
SFR
(Direct addressing only)
02FFh
02FFh
Expanded 768 bytes
(Accessed by direct
external addressing
mode, using the
MOVX instruction)
(XRAME=1)
IF XRAME = 1
and
DFLASHE = 1
Data Flash
Mapped as
External Memory
Use MOVX to Read
0000h
0000h
By default, after reset the expanded RAM area and the
data Flash areas are disabled. They are enabled by
setting the XRAME and the DFLASHE bits
(respectively) of the SYSCON register located at
address BFh in the SFR.
The DFLASHE and XRAME bits of the SYSCON
register define which area the MOVX instruction will
target:
DFLASHE
0
0
1
1
XRAME
0
1
0
1
MOVX
<= 2FFh
Ext. Memory
Int. RAM
Int. Data Flash
Int. RAM
MOVX
> 2FFh
Ext. Memory
Ext. Memory
Int. Data Flash
Int. Data Flash
Lower 128 bytes (00h to 7Fh, Bank 0 & Bank 1)
The lower 128 bytes of data memory (from 00h to 7Fh)
is summarized as follows:
o Address range 00h to 7Fh can be accessed in
direct and indirect addressing modes
o Address range 00h to 1Fh includes R0-R7
register areas
o Address range 20h to 2Fh is bit addressable
o Address range 30h to 7Fh is not bit
addressable and can be used for general-
purpose storage
Upper 128 bytes (80h to FFh, Bank 2 & Bank 3)
The upper 128 bytes of the data memory ranging from
80h to FFh can be accessed using indirect addressing
or by using the bank mapping in direct addressing
mode.
Expanded RAM Access Using the MOVX @DPTR
Instruction (0000-02FF, Bank4-Bank15)
The 768 bytes of expanded RAM data memory
occupies addresses 0000h to 02FFh. This can be
accessed using external direct addressing (i.e. the
MOVX instruction) or bank mapping direct addressing.
When indirect addressing executes the MOVX
@DPTR instruction, if the address is larger than 02FFh
and the data Flash is disabled (DFLASHE=0), the
VRS51C1100 will access off-chip memory in the
external memory space using the external memory
control signals.
The MPAGE Register (Extra Read Data
Pointer)
The VRS51C1100 features a second data pointer
called MPAGE, which is dedicated to data Flash and
external RAM read access using the MOVX @Ri
(I=0,1) instruction. The MPAGE register provides the
high byte of the address, while the contents of the Ri
register provides the low byte of the address. The
operation of the MPAGE register resembles that of the
______________________________________________________________________________________________
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page 11 of 50
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet VRS51C1100.PDF ] | |
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