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Número de pieza | TC74AC11P | |
Descripción | TRIPLE 3-INPUT AND GATE | |
Fabricantes | Toshiba Semiconductor | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de TC74AC11P (archivo pdf) en la parte inferior de esta página. Total 8 Páginas | ||
No Preview Available ! TC74AC11P/F/FN
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74AC11P,TC74AC11F,TC74AC11FN
Triple 3-Input AND Gate
The TC74AC11 is an advanced high speed CMOS 3-INPUT
AND GATE fabricated with silicon gate and double-layer metal
wiring C2MOS technology.
It achieves the high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low power
dissipation.
The internal circuit is composed of 4 stages including buffer
output, which provide high noise immunity and stable output.
All inputs are equipped with protection circuits against static
discharge or transient excess voltage.
Features
• High speed: tpd = 5.3 ns (typ.) at VCC = 5 V
• Low power dissipation: ICC = 4 μA (max) at Ta = 25°C
• High noise immunity: VNIH = VNIL = 28% VCC (min)
• Symmetrical output impedance: |IOH| = IOL = 24 mA (min)
Capability of driving 50 Ω
transmission lines.
• Balanced propagation delays: tpLH ∼− tpHL
• Wide operating voltage range: VCC (opr) = 2 to 5.5 V
• Pin and function compatible with 74F11
Pin Assignment
Note: xxxFN (JEDEC SOP) is not available in
Japan.
TC74AC11P
TC74AC11F
TC74AC11FN
Weight
DIP14-P-300-2.54
SOP14-P-300-1.27A
SOL14-P-150-1.27
: 0.96 g (typ.)
: 0.18 g (typ.)
: 0.12 g (typ.)
1 2007-10-01
1 page Package Dimensions
TC74AC11P/F/FN
Weight: 0.96 g (typ.)
5 2007-10-01
5 Page |
Páginas | Total 8 Páginas | |
PDF Descargar | [ Datasheet TC74AC11P.PDF ] |
Número de pieza | Descripción | Fabricantes |
TC74AC112F | DUAL J-K FLIP FLOP WITH PRESET AND CLEAR | Toshiba Semiconductor |
TC74AC112FN | DUAL J-K FLIP FLOP WITH PRESET AND CLEAR | Toshiba Semiconductor |
TC74AC112P | DUAL J-K FLIP FLOP WITH PRESET AND CLEAR | Toshiba Semiconductor |
TC74AC11F | TRIPLE 3-INPUT AND GATE | Toshiba Semiconductor |
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