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PDF IDT74LVC16823A Data sheet ( Hoja de datos )
| Número de pieza | IDT74LVC16823A | |
| Descripción | CMOS 18-BIT REGISTER | |
| Fabricantes | IDT | |
| Logotipo |  |
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IDT74LVC16823A
3.3V CMOS 18-BIT REGISTER WITH 3-STATE OUTPUTS
3.3V CMOS
18-BIT REGISTER
WITH 3-STATE OUTPUTS
AND 5 VOLT TOLERANT I/O
INDUSTRIALTEMPERATURERANGE
IDT74LVC16823A
FEATURES:
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• CMOS power levels (0.4µ W typ. static)
• All inputs, outputs, and I/O are 5V tolerant
• Supports hot insertion
• Available in SSOP, TSSOP, and TVSOP packages
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Reduced system switching noise
DESCRIPTION:
The LVC16823A 18-bit register is built using advanced dual metal CMOS
technology. This high-speed, low-power register is ideal for use as a buffer
register for data synchronization and storage. The Output Enable (OE) and
clock (CLK) controls are organized to operate each device as two 9-bit
registers or one 18-bit register with common clock. Flow-through organi-
zation of signal pins simplifies layout. All inputs are designed with hysteresis
for improved noise margin.
All pins of the LVC16823A can be driven from either 3.3V or 5V devices.
This feature allows the use of this device as a translator in a mixed 3.3V/
5V supply system.
The LVC16823A has been designed with a ±24mA output driver. The
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
APPLICATIONS:
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
FUNCTIONAL BLOCK DIAGRAM
1OE
1CLR
1CLK
1CLKEN
2
1
56
55
54
1D1
27
2OE
2CLR 28
2CLK 29
2CLKEN 30
RR
CC
DD 3 1Q1
2D1 42
RR
CC
DD 15 2Q1
TO EIGHT OTHER CHANNELS
TO EIGHT OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
© 1999 Integrated Device Technology, Inc.
1
APRIL 1999
DSC-4573/2
1 page  
IDT74LVC16823A
3.3V CMOS 18-BIT REGISTER WITH 3-STATE OUTPUTS
INDUSTRIALTEMPERATURERANGE
TEST CIRCUITS AND WAVEFORMS
TEST CONDITIONS
Symbol VCC(1)= 3.3V±0.3V VCC(1)= 2.7V
VLOAD
6
6
VIH 2.7
2.7
VT 1.5
1.5
VLZ 300
300
VHZ 300
300
CL 50
50
VCC(2)= 2.5V±0.2V
2 x Vcc
Vcc
Vcc / 2
150
150
30
Unit
V
V
V
mV
mV
pF
VCC
VIN
Pulse (1, 2)
Generator
VOUT
D.U.T.
500Ω
VLOAD
Open
GND
RT
500Ω
CL
Test Circuit for All Outputs
LVC Link
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.
SAME PHASE
INPUT TRANSITION
OUTPUT
tPLH
OPPOSITE PHASE
INPUT TRANSITION
tPLH
tPHL
tPHL
Propagation Delay
VIH
VT
0V
VOH
VT
VOL
VIH
VT
0V
LVC Link
CONTROL
INPUT
ENABLE
tPZL
DISABLE
tPLZ
OUTPUT
NORMALLY
SWITCH
CLOSED
LOW
tPZH
OUTPUT SWITCH
NORMALLY OPEN
HIGH
VLOAD/2
VT
tPHZ
VT
0V
VIH
VT
0V
VLOAD/2
VOL+VLZ
VOL
VOH
VOH-VHZ
0V
LVC Link
Enable and Disable Times
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
SWITCH POSITION
Test
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other Tests
Switch
VLOAD
GND
Open
INPUT
OUTPUT 1
OUTPUT 2
tPLH1
tPHL1
tSK (x)
tSK (x)
VIH
VT
0V
VOH
VT
VOL
VOH
VT
VOL
tPLH2
tPHL2
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
Output Skew - tSK(X)
LVC Link
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS
CONTROL
SYNCHRONOUS
CONTROL
tSU tH
tREM
tSU tH
Set-up, Hold, and Release Times
VIH
VT
0V
VIH
VT
0V
VIH
VT
0V
VIH
VT
0V
LVC Link
LOW-HIGH-LOW
PULSE
HIGH-LOW-HIGH
PULSE
tW
Pulse Width
VT
VT
LVC Link
5
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet IDT74LVC16823A.PDF ] | |
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