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PDF SED1336 Data sheet ( Hoja de datos )

Número de pieza SED1336
Descripción CMOS GRAPHIC LCD/TV CONTROLLER
Fabricantes ETC 
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No Preview Available ! SED1336 Hoja de datos, Descripción, Manual

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SED1336
s DESCRIPTION
CMOS GRAPHIC LCD/TV CONTROLLER
For Medium-Scale LCD
Output to LCD-Screen
Virtual Screen Display RAM
Enhanced Control Function
•• Simultaneous LCD & TV Display
The SED1336 is a CMOS low-power dot matrix liquid crystal graphic display controller with built-in TV
support. The built-in TV support IC is capable of displaying characters and graphic images simultaneously
on TV monitors and flat panels.
The SED1336 has a built-in TV control circuit that generates either NTSC or PAL system synchronous
signals, memory. The device stores the display data in external SRAM that is sent by an 8-bit microcomputer,
and generates all the control signals required by the LCD drivers.
The controller incorporates an internal character generator ROM which supports user-defined characters. An
external CG ROM can also be supported to provide additional characters.
The SED1336 can be interfaced to high-speed microprocessors such as the Intel 80xx family or the Motorola
68xx family. The controller supports a set of commands that allow the user to create a layered display of
characters and graphics.
s FEATURES
Low-power CMOS fabrication
Compatible with both Intel 80XX and Motorola
68XX high-speed MPU
Display duty:
LCD ............... 1/2 to 1/256 can be selected
TV ...................................... 256 × 200 dots
Internal and external character generator ROM
Simultaneous LCD and TV operation
s SYSTEM BLOCK DIAGRAM
Selectable display synthesis
Programmable cursor movement
Multimode display:
2 layers of overlapping character and graphic
3 layers of overlapping graphic
Supports 64K bytes of memory
Single power supply ..................... 3.0V to 5.5V
Package ................... Plastic QFP6-60 pin (F0A)
DATA
CPU CONTROL
SED1336F
SRAM
153
MONO LCD
TV

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SED1336 pdf
SED1336
Parameter
Supply voltage
Register data retention voltage
Input leakage current
Output leakage current
Operating supply current
Quiescent supply current
Oscillator frequency
External clock frequency
Oscillator feedback resistance
TTL
HIGH-level input voltage
LOW-level input voltage
HIGH-level output voltage
LOW-level output voltage
CMOS
HIGH-level input voltage
LOW-level input voltage
HIGH-level output voltage
LOW-level output voltage
Open-drain
LOW-level output voltage
Schmitt-trigger
Rising-edge threshold voltage
Falling edge threshold voltage
VDD = 3.0 to 4.5V, VSS = 0V, Ta = –20 to 75°C
Symbol
Condition
VDD See note 8.
VHO
ILI VI = VDD. See note 6.
ILO VI = VSS. See note 6.
Iopr VDD = 3.5V. See note 4.
See note 4.
IQ
Sleep mode,
VOSC1 = VCS = VRD = VDD
fOSC Measured at crystal,
fCL 47.5% duty cycle.
Rf See note 7.
Min
3.0
2.0
1.0
1.0
0.7
Typ
3.5
0.05
0.10
3.5
0.05
Max Unit
4.5 V
6.0 V
2.0 µA
5.0 µA
mA
7.0
20.0 µA
8.0 MHz
8.0 MHz
3.0 M
VIHT
VILT
VOHT
VOLT
See note 1.
See note 1.
IOH = –3.0 mA.
See note 1.
IOL = 3.0 mA. See note 1.
0.8VDD
VSS
2.4
— VDD V
— 0.2VDD V
——
V
— VSS + 0.4 V
VIHC
See note 2.
0.8VDD
VDD
V
VILC
See note 2.
VSS — 0.2VDD V
VOHC IOH = –2.0 mA. See note 2. VDD – 0.4 — — V
VOLC IOH = 1.6 mA. See note 2. —
— VSS + 0.4 V
VOLN IOL = 6.0 mA. See note 5. —
— VSS + 0.4 V
VT+
See note 3.
0.5VDD 0.7VDD 0.8VDD
V
VT–
See note 3.
0.2VDD 0.3VDD 0.5VDD
V
Notes:
1. D0 to D7, A0, CS, RD, WR, VD0 to VD7, VA0 to VA15,
VRD, VWR and VCE are TTL-level inputs.
2. SEL1 and NT/PL are CMOS-level inputs. YD, XD0 to
XD3, XSCL, LP, WF, YDIS and CLO are CMOS-level
outputs.
3. RES is a Schmitt-trigger input. The pulsewidth on RES
must be at least 200 µs. Note that pulses of more than a
few seconds will cause DC voltages to be applied to the
LCD panel.
4. fOSC = 10 MHz, no load (no display memory), internal
character generator, 256 × 200 pixel display. The operat-
ing supply current can be reduced by approximately 1 mA
by setting both CLO and the display OFF.
5. SNC and VSD are n-channel, open-drain outputs. The
voltage on the outputs should not exceed VDD as internal
diodes connect the pins to VDD.
6. VD0 to VD7 and D0 to D7 have internal feedback circuits
so that if the inputs become high-impedance, the input
state immediately prior to that is held. Because of the
feedback circuit, input current flow occurs when the
inputs are in an intermediate state.
7. Because the oscillator circuit input bias current is in the
order of µA, design the printed circuit board so as to
reduce leakage currents.
8. VDD = 2.7 to 4.5V (SED1335F)
157

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SED1336 arduino
° LCD Output Timing
The following characteristics are for a 1/64 duty cycle.
Row 62 63 64 1 2 3 4
60 61 62 63 64
LP
1 frame time
YD
WF
WF
Row 64
LP
1 line time
Row 1
Row 2
XSCL
XD0 to XD3 (14) (15) (16)
(1)
(15) (16) (1) (2) (3)
(15) (16) (1)
XSCL
tr
XD0 to XD3
LP
tWX
tDS
tLD
WF(B)
YD
tf
tDH
tLS
tWL
tCX
tDHY
tDF
163
SED1336

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